hello,how could i introduce a delay on the output of a desing? i am using altera quartus 2 (cyclone2)
If you want a delay, you need a clock and a counter. There is no other way in fpga.i have attach my design. i want to add a delay on the input or output. is it anyways to do it schematicly?
Look here on a basic VHDL rundown, and especially here.hello,
can you say me please where is the problem??
and give us an exemple of program with clock and counter !
would it be a schematic counter and how would i set the cloc since i am using quartus software and i am testing it using the altera DE2 boad.If you want a delay, you need a clock and a counter. There is no other way in fpga.
Except maybe for delay locked loops which are used for clock buses, but this is for delays in the ns range, which I presume is way shorter than you want.
please how can i derived a clock from the main one and how can design it. i am new on using quartus and sorry to ask to many question but i would appreciated your helpThe FPGA allways has some external clock and runs on a certain frequency, typically 50MHz, that is clock period of 20ns. Let's say you want a delay of 1ms, so you need to use a counter and count to 1ms/20ns, that is 50,000 clock cycles.
You could also make another clock derived from the main clock, say dividing it by 1000, so that the new clock runs on 50kHz, then you would count to just 50 clock cycles.
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