Hi

I have tried to create a little logic circuit in a simulator.

Its a shift register using a d flip flop, I have seen quite a few examples of this on the web.

Anyway I create a d flip flop with logic gates, I have tried a couple of different gate configurations from online examples. Here is one I am using at moment.
http://i1025.photobucket.com/albums/y319/duxbuz/Dflipflop_zps34ff9454.jpg

I then built up my circuit using my d flip flop and I also used a d flip flop ic that was part of the circuit simulator I am using Logisim.

http://i1025.photobucket.com/albums/y319/duxbuz/shiftregister_zpsca1f066e.jpg

The logisim d flip flop works fine, mine doesn't. So am wondering what I have got wrong with my d flip flop

Could anyone have a look for me please?

Thanks

 

hi dux,
It would helpful if you could annotate the non working logic drawings with pin numbers or some other ID.

E

 

Thanks for looking

I think the bottom shift register has D and Q labelled.

Mine is just the same inputs and outputs, but upside down. Basically the ones with the LEDs on are data inputs and the others are the clock.

I was thinking it would be the d flip flop gate that might be the problem circuit.

Cheers

 

Your FF is commonly called a gated D-latch. It responds to the D input whenever the enable (clock) signal is high (level sensitive). The Logisim FF is edge-triggered which means it only responds to the D input during one of the clock edges (either going high or going low) of the clock signal and doesn't respond otherwise.

For your shift register to respond properly it needs an edge-triggered FF. Here's a description of the various types of latches and flip-flops.

 

Thanks thought something was amiss. So a quick look online I am guessing I can make mine edge triggered with a few more gates?

 

Great thanks. It works now. I used a different schematic from that wiki article you suggested to look at:
http://en.wikipedia.org/wiki/File:Edge_triggered_D_flip_flop.svg