I am having difficulty with the following problem:

Given a 100-MHz clock cycle, derive a circuit using D flip flops to generate 50-MHz and 25-MHz clock signals. Draw a timing diagram for all three clock signals, assuming reasonable delays.

Ok, I believe I will need three D Flip Flops, using D for the input, K for the clock, and Q and !Q for the output. I think I need to either connect the Q or !Q output back to the input into D. I am not sure which...and I don't know if it really matters. Afterwards I can move the line from either Q or !Q to gather the output frequencies. Am I on the right track? Thanks for all help.

Edit: After rethinking the situation I believe I would need two D Flip-Flops instead. The first would output 50Mhz and the second would halve the 50MHz to 25 MHz.

 

Feed !Q back to D to give divide-by-two with the clock input at 100MHz on the first stage to give 50MHz output at Q or !Q. The 50MHz (either at Q or !Q) would wire to the clock input for the second 25MHz output stage. Again wire !Q for the second stage to D input of the second stage.

 

Thank you for the help.