verilog code for d flip flop with positive edge

module d_ff( q, q_bar,d, clk);
input d ,clk;
output q,q_bar;
reg q,q_bar;
always@ (posedge clk)
begin
q <= d;
q_bar <= !d;
end
endmodule

q <=1'b0;
q_bar <=1'b1

what does it mean

 

q <=1'b0;
q_bar <=1'b1

what does it mean

q <=1'b0;

This assigns a 0 to the output signal 'q'.

q_bar <=1'b1

This assigns a 1 to the output signal 'q_bar '.

Now, If you place that into an always block with the sensitivity list being the posedge od a clock, then these assignments will take place at the positive edge of the clock.

Here are some comments to help out a little in your understanding

module d_ff( q, q_bar,d, clk);
input d ,clk;
output q,q_bar;
reg q,q_bar; // make q and q_bar register types

always@ (posedge clk) // do the following when the positive edge of 'clk' comes.
begin
    q <= d; // assign(non-blocking) d to q on the positive edge of the clock(clk)
    q_bar <= !d; //assign(non-blocking) inverse of d to q on the positive edge of the clock(clk)
//Note: these assignments happen concurrently at the positive edge of the clock.
end
endmodule

 

q <=1'b0;

This assigns a 0 to the output signal 'q'.

q_bar <=1'b1

This assigns a 1 to the output signal 'q_bar '.

Now, If you place that into an always block with the sensitivity list being the posedge od a clock, then these assignments will take place at the positive edge of the clock.

Here are some comments to help out a little in your understanding

module d_ff( q, q_bar,d, clk);
input d ,clk;
output q,q_bar;
reg q,q_bar; // make q and q_bar register types

always@ (posedge clk) // do the following when the positive edge of 'clk' comes.
begin
    q <= d; // assign(non-blocking) d to q on the positive edge of the clock(clk)
    q_bar <= !d; //assign(non-blocking) inverse of d to q on the positive edge of the clock(clk)
//Note: these assignments happen concurrently at the positive edge of the clock.
end
endmodule

ok thanks for replay


D flip flop function table


d clk q q_bar
0 ↑ 0 1
1 ↑ 1 0
0 ↑ 0 1
1 ↑ 1 0


now I want to write assign statement for this table

q <= 1b'0
Q_bar <= 1'b1
q <= 1b'1
q_bar <= 1b'0
q <= 1b'0
Q_bar <= 1'b1

is it correct ?

 

ok thanks for replay


D flip flop function table


d clk q q_bar
0 ↑ 0 1
1 ↑ 1 0
0 ↑ 0 1
1 ↑ 1 0


now I want to write assign statement for this table

q <= 1b'0
Q_bar <= 1'b1
q <= 1b'1
q_bar <= 1b'0
q <= 1b'0
Q_bar <= 1'b1

is it correct ?

Your table is repeating itself, but yes, this is the correct functionality.

Note that the D flip-flop is referred to as the "delay" flip flop, meaning the output will be the input delayed by one clock cycle. Or, to look at it another way, the current state of D determines the state of Q at the next sensitive clock edge (e.g. Positive edge).

All that is to say that what you assign to Q should rely on D.

Your assignments, as they are, won't do anything - you have multiple, conflicting drivers for q and q_bar. If you want to do it that way, you need to test D and use its value to determine what is assigned to q/q_bar.

 

Is it true for d flip flop with positive edge

module d_ff( q, q_bar,d, clk);
input d ,clk;
output q,q_bar;
reg q,q_bar;
always@ (posedge clk) begin
 q <= 1b'0
 Q_bar <= 1'b1
 q <= 1b'1
 q_bar <= 1b'0             
end endmodule

No. Remember, q is dependent on what d was before the clock edge. This means d must influence what q becomes, with q_bar simply being !q.

The stuff inside the always block is executed concurrently, so you cannot drive the same signal to two different states at the same time.

D flip flop truth table positive edge

d clk q q_bar
0 ↑ 0 1
1 ↑ 1 0

Yes, this is more like it.

I have doubt that one flip flop store only bit 0 or 1

This its what a flip-flop does.

 

Your table is repeating itself, but yes, this is the correct functionality.

Note that the D flip-flop is referred to as the "delay" flip flop, meaning the output will be the input delayed by one clock cycle. Or, to look at it another way, the current state of D determines the state of Q at the next sensitive clock edge (e.g. Positive edge).

All that is to say that what you assign to Q should rely on D.

Your assignments, as they are, won't do anything - you have multiple, conflicting drivers for q and q_bar. If you want to do it that way, you need to test D and use its value to determine what is assigned to q/q_bar.

module d_ff( q, q_bar,d, clk); 
input d ,clk; 
output q,q_bar; 
reg q,q_bar; 
always@ (posedge clk)                 
 begin                            
q <= 1b'0
Q_bar <= 1'b1
q <= 1b'1
q_bar <= 1b'                  
 end 
endmodule

D flip flop table
d clk q q_bar
0 ↑ 0 1
1 ↑ 1 0

I want to ask the table and code i have posted is true for synchronous D flip flop with positive edge

 

Did you delete your previous post and repost it with slightly different wording?

Anyway, you seem a little confused about how to use the always block, see this page to get some more insight.

 

sorry for double post because I was editing my old post I am student if my teacher ask me write verilog code for D flip flop then can I write code that I have posted first