For a D clocked flip, I know that D must be high before the clock goes high. (assuming PGT). However, what will happen if they are both triggered high at the same time?

 

There are two critical times "set-up, tsu" and "hold", thold. If not met then expected output change is not guaranteed. There is also a minimum clock pulse low width requirement for a maximum clock frequency.

tsu - the time the D input must have been stable & high (or low) before the clock input 50% low-high transition point. For the HEF4013B Dual D type - CMOS Family - this is quoted (the one manuf. by Philips) as at least 40ns at 5V VDD.

thold - the time the D input must remain stable & high (or low) after the clock input 50% low-high transition point. For the same chip this is at least 20ns at 5V VDD.

Hope that helps.