CW due soon, :-/

Hi all,



This is my first post so go easy please lol.


I am currently in my final year of MEng Electronic Engineering, and have been giving the module on ASIC's and Digital Design, now I must say that i really cannot grasp this module what so ever and find the work extremely difficult. Usually i am very good with deadline and all that, but Thesis research and class test have taken up a lot of my time.


The program I am (trying) to using is Quatus II 9.1 and the question i have been given is below:



Design two decade counters that are cascaded to produce an output from 00 to 99 on 8 digital outputs. Arrange an input that can stop the count when brought low – use a switch on the development board for this purpose. Drive this design from your 1 Hz source.


Any help with this guys & girls would be really great, thanks for your time and consideration.



Conal McCool (conalmccool@hotmail.com)