I studied crossing clock domains a while back. Plenty of methods to do this. My question is if a clockdomain crossing architecture is needed with harmonic clocks with the same clock origin.
Example:
FPGA
Single 20MHz external clock is PLL'd to provide 200MHz.
The 200MHz clock is divided by 4 within the clock tree to also provide 50MHz.
Most of the chip operates at 50MHz to limit power consumption.
A small section of the chip operates at 200MHz.
There is some data passed between the low-speed clock to the high-speed clock, but not vice versa.
Does the designer need to provide clock domain crossing interface in this situation?
Example:
FPGA
Single 20MHz external clock is PLL'd to provide 200MHz.
The 200MHz clock is divided by 4 within the clock tree to also provide 50MHz.
Most of the chip operates at 50MHz to limit power consumption.
A small section of the chip operates at 200MHz.
There is some data passed between the low-speed clock to the high-speed clock, but not vice versa.
Does the designer need to provide clock domain crossing interface in this situation?