Crossing clock domains - Question

Thread Starter


Joined Sep 16, 2012
I studied crossing clock domains a while back. Plenty of methods to do this. My question is if a clockdomain crossing architecture is needed with harmonic clocks with the same clock origin.

Single 20MHz external clock is PLL'd to provide 200MHz.
The 200MHz clock is divided by 4 within the clock tree to also provide 50MHz.
Most of the chip operates at 50MHz to limit power consumption.
A small section of the chip operates at 200MHz.
There is some data passed between the low-speed clock to the high-speed clock, but not vice versa.

Does the designer need to provide clock domain crossing interface in this situation?


Joined Dec 13, 2021
If you use CDC, then you need to tell the tools not to worry about the clock phase
If you do not use CDC, you need to be able to tell the tools of the relationship between the two clocks

Depending upon the clock circuit of the FPGA,
one clock might arrive at a register much different to the other clock,
and the placer needs to now to put the two registers close together.

Some FPGAs allow you to use a local clock buffer to divide a clock by two,
but it gets interesting,

The "easy" answer is to either
a) use CDC
b) clock all reg at the faster rate, and use an enable to clock some registers at the lower rate.