Hi all,
So I am designing a mark II graphics card (320 x 200) on a CPLD (Xilinx 9572XL) and was wondering if a schematic is more or less "efficient" than VHDL. In other words, does a well designed schematic use fewer macrocells than VHDL?
I know that schematics are converted into VHDL but is that VHDL more efficient that the user programmed VHDL?
All the best,
Robin
So I am designing a mark II graphics card (320 x 200) on a CPLD (Xilinx 9572XL) and was wondering if a schematic is more or less "efficient" than VHDL. In other words, does a well designed schematic use fewer macrocells than VHDL?
I know that schematics are converted into VHDL but is that VHDL more efficient that the user programmed VHDL?
All the best,
Robin