Looking for an example for this kind of situation explained by my professor for an upcoming test.
We will be designing in Quartus using block diagram/schematic file.
3 counters: (can use LPM)
counter1) holds data with a specific count sequence
counter2) rolls over and clocks the shift registers
counter3) rolls over and is a divide by counter that is counting down the system clock to a reasonable level
2 registers (SIPO and PISO)
-clocks data from data register parallel in to PISO
-then shifts serially to SIPO
-then clocking it out parallel out to board
We will be designing in Quartus using block diagram/schematic file.
3 counters: (can use LPM)
counter1) holds data with a specific count sequence
counter2) rolls over and clocks the shift registers
counter3) rolls over and is a divide by counter that is counting down the system clock to a reasonable level
2 registers (SIPO and PISO)
-clocks data from data register parallel in to PISO
-then shifts serially to SIPO
-then clocking it out parallel out to board
