Hey, guys. This is my first post on the forum so I apologize if I don't include something that "should" be provided in a question.

To the point: Using a standard counter-4 and as few logic gates as possible, I am supposed to build a counter that counts the sequence: 3,6,12,8,... etc.

I have figured out that I need a NAND gate with Q0Q1'Q2'Q3 connected to the Load. When load is 1, load D0-D3 = 1100. UP will be always 1, and the CLK connected to the clock. I realize this is what shift registers do and this is in fact another part of the homework question - to implement the above sequence using a 4-bit left-shift register, but I know how to do this one.

My question is about the counter: I don't really see the logic that should be applied...

It looks like D0 = Q2, D1 = Q3', D2 = Q0' and D3 = Q1' but I don't know what to do with it.

Cheers!!

--Rafal

To the point: Using a standard counter-4 and as few logic gates as possible, I am supposed to build a counter that counts the sequence: 3,6,12,8,... etc.

I have figured out that I need a NAND gate with Q0Q1'Q2'Q3 connected to the Load. When load is 1, load D0-D3 = 1100. UP will be always 1, and the CLK connected to the clock. I realize this is what shift registers do and this is in fact another part of the homework question - to implement the above sequence using a 4-bit left-shift register, but I know how to do this one.

My question is about the counter: I don't really see the logic that should be applied...

It looks like D0 = Q2, D1 = Q3', D2 = Q0' and D3 = Q1' but I don't know what to do with it.

Cheers!!

--Rafal

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