What is the minimal logic circuit to count the number of logic ones in a 7 bit input, using only half adders and full adders of one bit only(both)?

Thanks a lot

 

Sorry, this isn't, "Free Homework Answers". It's, "Homework Help". Tell us what you know about solving the problem and we'll start from there.

 

The same answer for everything else:

42

 

As #12 indicated, you need to show YOUR efforts to solve YOUR homework problem. We can then help guide you from where you are to where you need to end up.

 

My Ouija board says 7...

 

Sorry, you are right.. I should explain myself.
I have been thinking ,as a beginning, using 2 full adders.
Lets say the number would be presented as a0a1...a6

So the first FA will get a0,a1,a2
The second FA a3,a4,a5
Than using another FA with the a6 bit, and connect the sums of the two, and then use another FA to the Carry of the 2 FA..

But I am not sure its best solution..

Any ideas?

Thanks

 

If the 7-bit input is loaded into a shift register you can examine the bits one at a time with seven clock pulses. You need a 3-bit counter with an enable. You have a state machine that examines a data bit and increments the counter if it is a '1' and holds the present state it it is a '0. The states would be:
{LOAD, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, DONE}
Input would be START and outputs would be the 3-bit counter

 

Thanks but I am not allowed to use what you have mentioned..
I can use HA and FA of one bit only

 

Sorry, you are right.. I should explain myself.
I have been thinking ,as a beginning, using 2 full adders.
Lets say the number would be presented as a0a1...a6

So the first FA will get a0,a1,a2
The second FA a3,a4,a5
Than using another FA with the a6 bit, and connect the sums of the two, and then use another FA to the Carry of the 2 FA..

But I am not sure its best solution..

Any ideas?

Thanks

I think you are on the right track. It's bit hard to follow which FAs you are talking about when. It would help if you could through a sketch together (Something simple in Paint will do fine) to make it all clear.

But I think you have what came immediately to my mind, which involves four FAs.

 

If the 7-bit input is loaded into a shift register you can examine the bits one at a time with seven clock pulses. You need a 3-bit counter with an enable. You have a state machine that examines a data bit and increments the counter if it is a '1' and holds the present state it it is a '0. The states would be:
{LOAD, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, DONE}
Input would be START and outputs would be the 3-bit counter

1) His constraints won't let him use anything by Half Adders and Full Adders.

2) It can be done with considerably less hardware than this.

 

If you want to count the number of ones in order to determine the parity simply use a parity encoder.

 

If you want to count the number of ones in order to determine the parity simply use a parity encoder.

But that's not what he's trying to do. The OP's description of what he is trying to do and the constraints he is working under were actually among the better descriptions we have seen lately.

 

If you search my older posts you'll find the answer, the underlying math, even a schematic.