my idea is that you send a signal to set the flip-flop to HIGH and send the same signal to an AND gate with a resistor to delay it, before it resets the flip-flop to LOW... and thus one should be able to control the lenght of a signal.


would this work?


i've had very little luck and experience with flip-flops, i must admit..
but then again i also had little luck with the other chips that i am now starting to get.

 

No. If both SET and RESET of a 4013 are both active at the same time, it goes into a confused state where both Q and notQ are active at the same time.
If you put a capacitor in series with each of the set and reset inputs (small value, 10nF or so) and a resistor from each of set and reset to ground (10k or so), then it would work.
The capacitors would give a brief positive-going pulse on SET when the SIGNAL_IN goes high, and a brief positive-going pulse on RESET when the output of the 4081 goes high, so that SET and RESET are not both active at the same time.
By the way, if this is a real circuit, don't forget to connect D and Clock to ground.

Also worth a try, if you are experimenting: keep the original circuit but connect D high, connect SIGNAL_IN to CLOCK.
Connect SET to ground. Leave RESET where it is.

 

How to make a pulse,
Take a square wave, split in two, delay one side, put the delayed and none delayed signals into a gate.
if the gate as say a XOR, you get a pulse when the to inputs are different,

Inverting the delay line, and chgianging the gate , allows rising or falling edge detection.

How to delay one signal ?

options,
put a few gates in series,
long track on the board,
a delay line
and RC circuit ( as you have )

Remember to drive with a low impedance the square wave, such as using another buffer.

https://electronics.stackexchange.c...s-signal-into-a-short-pulse-using-logic-gates

 

As above, your circuit has problems. It is easy to fix.

1. Fill in the reference designators for all components. ? is not a designation.

2. Delete the 4013.

2. Tie together both inputs of the 4081. This is now a non-inverting buffer.

3. Reverse the positions of the resistor and capacitor.

Now, when the input signal goes high, it is coupled to the gate through the capacitor, and the input to the gate goes high. The resistor starts discharging the capacitor. After approx. 0.7 x R x C, the input voltage goes below the gate's input transition level, and the output of the gate changes state.

That is the most basic circuit, and is good enough to demonstrate the principle of an R-C delay network. BUT it has a potential problems.

Depending on the amount of delay you want, the gate's input voltage might be changing pretty slowly. The gate basically is a high gain linear amplifier. As the input voltage crosses the transition region, the gate amplifies voltage noise (everything has noise) at the input and produces a noise burst at the output. The solution is adding a large value resistor from the gate's output to its input, creating hysteresis.

Time for some homework:

https://en.wikipedia.org/wiki/Hysteresis#Electronic_circuits

The other problem is the capacitor overdriving the gate input. The solution is adding a small signal diode across the resistor, but that is another topic.

ak

 

Use a monostable multivibrator such as 74HC123, CD4528, CD4538.

 

..... or if you want to use the 4013, you can eliminate the AND gate and reset the 4013 by driving the RC combo with Signal_out. That would, though, need Signal_in to be less duration than your required pulse width.

 

..... or if you want to use the 4013, you can eliminate the AND gate and reset the 4013 by driving the RC combo with Signal_out. That would, though, need Signal_in to be less duration than your required pulse width.

Good idea, and if you connected SIGNAL_IN to CLOCK and D to V+, it would work with any length of input signal!

 

thank you all...!

i will be back with more questions later..