"Design of 8-to-1 MUX with enable, using the 74153 dual 4-to-1 multiplexers with enable (dual means that two 4-to-1 multiplexers in one IC package) and an inverter. Write Verilog code for the 8x1 multiplexer, which uses the Verilog code for 4-to-1 multiplexer with enable.*" My lab task is this, however I am stuck. I can design the 8x1 mux with a dual 4x1 mux and a 2x1 mux but I have no idea how am I supposed to do it with an inverter.

Please help me thanks.

 

So show how you would do it with a dual 4:1 MUX and a 2:1 MUX and we can use that as a starting point and guide you toward how to see that you can use an inverter instead of the 2:1 MUX. Although I think you will need some additional components, either an OR gate or some passive components to make a wired-OR.

Here's a hint. What is the role of the 2x1 MUX? How else could this task be accomplished when your have 4:1 MUXes that have output enables?

 

OK, first of all thanks for your reply. I think that I have to combine and select between the two outputs of the 4x1 outputs in order to have a single output but I don't know how to do it. I've mailed my professor and he is saying that the lab specification is correct and I am only allowed to use two 4x1 multiplexers and one inverter. But the two multiplexers are also 74153 dual 4x1 multiplexer(their selects are common). Please give me an idea I cannot deal with this at this point.

Thank you very much...

 

Ask your professor to confirm that the outputs of the 4:1 MUXes are always active, even when disabled, meaning that when one of them is disabled that the output for that MUX is actively driven LO instead of being placed in a high-Z state.

 

I've figured it out so I added a third select input and connected to both enables of the 4x1 multiplexers, with an inverter on the second. So for the first 4 combinations the first multiplexer is on and the output depends on it. However, starting from the "100" it disables the first mux and depends on the second 4x1 mux.

 

Is it right?

 

But how do you combine the two outputs from the two 4:1 MUXes into the single output of the 8:1 MUX?

 

yeah I also thought about that, it still seems that we need an OR gate to combine the two outputs. Or maybe in the 74153 IC, when one of the multiplexers is disabled, it doesn't give an output at all.

 

yeah I also thought about that, it still seems that we need an OR gate to combine the two outputs. Or maybe in the 74153 IC, when one of the multiplexers is disabled, it doesn't give an output at all.

I suspect that is what you instructor thinks. But go read the data sheet and be prepared to refer to it when and if your instructor tells you something that contradicts it.

 

yeah I also think that he is thinking like that. Also the task asks me to write the code for the 8x1 mux using the design with the inverter and at that point are there any solutions to completely disable a 4x1mux's output in Verilog? So that I will not need an OR gate for the final output?

 

You can set the output to Z. Some synthesis tools may not like that, but the simulators shouldn't have a problem with it. Also, some synthesis tools can figure out how to deal with it even on hardware that doesn't have three-state outputs, but that's a bit hit-and-miss.

Just be aware that as soon as you do that, you are NOT using a 74153 any longer. You are using a 74BOB (i.e., a custom part that does not necessarily behave like any standard part that you might as well call a "bob" gate.