Hi again everyone

My aims are to make a 2 bit synchronous sequential counter that counts 0,1,2,3 and 4 in binary. I have produced the truth tables, Karnaugh maps and have the following expressions which result in:
1) an XOR gate
2) a NOT gate.

My issue is that I do not know how to connect the XOR and NOT gate to the D- flip-flops.

I think the XOR will go into 'D' on the flip flop and the NOT into the second 'D' on the flip flop. I am not sure how to wire the rest of the circuit. How would I go about it?

 

Post the truth table. Can't help you otherwise.

From the truth table you should be able to determine the proper connections of the components.

 

Sorry, I have attached the truth table For the D type flip flop.

 

Keep in mind that a 2-bit counter counts from 0 up to 3, not 4. Other than that, why do you try to re-invent the wheel?
http://www.allaboutcircuits.com/vol_4/chpt_11/3.html

 

I am still confused. This is what I understand so far...
For synchronous counters, the clocks are common.
The LSB switches from low to high, and that toggles the next bit. (for 2 bits and say for 4 bits, there will be a divide by 8 output).

Am I correct in saying that the XOR and NOT gates can be used with the D flip flops to make 2 bit synchronous counter? And am I correct to say that the 'D' on the two D flip flop block diagrams connect to XOR nd NOT, one for each? I want the counter to continue after it counts binary 3 to would this require feedback e.g. Q' connected to D ?

To summarise my issue, I have no idea what to do with Q. I don't know what the importance of Q' is. Sorry for my rant, I thought I should just express all my thoughts in one go.

 

Q is the normal output of the FF and Q' is the inverted output of the FF.

The truth-table sequence you want for a 2-bit counter with the required D inputs shown are:



Remember that the state of Q1 and Q2 is shown after the clock transition and is determined by the state of D1 and D2 prior to the clock transition.

Since FF1 just flips on alternate clocks, you can connect its Q' (inverted) output directly to its D input to achieve that.

FF2 goes high after FF1 goes high and stays high until both FFs are high. Thus you can connect the Q output of FF1 to one input of an XOR gate, and the Q output of FF2 to the other XOR gate input. The output of the XOR gate goes to FF2 D input. Thus FF2 D input is high when the FF1 Q output is high (01) or FF2 output is high (10) but low otherwise (00 & 11). This causes FF2 to follow the desired sequence.

 

Thankyou so much carl. Would I then conmect a not gat to Q' to read my output signal?

 

Q is the normal output of the FF and Q' is the inverted output of the FF.

You shouldn't need the extra gate (NOT). This should also answer your question regarding the purpose of the Q output.

 

I was thinking that a not gate was missing but by linking Q' and D is basically the not gate.

Would it be possible if someone could draw a timing diagram for D, Q' Q for FF1 and D Q and Q'. I am still trying to get my head around the propogation of the signals and also, i wouldnt be able to build an altered circuit. I get what has been explained and will noe know that connecting Q' to D produces an alternating signal, but I wouldnt be able know that if I was not told.

 

A D-FF's operation is quite simple. When the clock edge occurs (positive for a positive edge triggered device) the Q output goes to the state of what the D input is prior to the clock edge. Thus if D is logic 1, Q will change to logic 1 after the clock edge. If D stays at 1, then Q will also stay at one after the next clock edge. Similarly if D is logic 0, then Q goes to logic 0 after the clock edge. The Q' output is always the inverse of Q. Edit: The D value has no effect on the Q output between clock edges.

From that you should be able to draw your own timing diagram.

 

I think Im finally getting it all now. Thanks for you help crutschow and to everyone else!