confusion about FOSC of PIC18F4550 set up

Thread Starter

tuanvoi

Joined Oct 31, 2008
56
Hi all,
I'm using USART of PIC18F4550 to transmit data via bluetooth eb301 from www.a7eng.com. My bluetooth factory default is 9600 baud rate, no parity and no flow control. My problem is I don't know to how to set up the PIC18F4550 properly so that the PIC18F4550 and bluetooth can be synchronized. So, i can send and receive the data correctly from bluetooth eb301 devices. Could you please help me on this, thank you!
 

mik3

Joined Feb 4, 2008
4,843
To synchronize to devices you need to drive them with the same clock, otherwise you need to use other techniques to transfer data between them like interrupts or port polling.
 

Thread Starter

tuanvoi

Joined Oct 31, 2008
56
thanks thatoneguy and mik3
Could you please give me more details about "interrupts or port polling"? Thanks
For the register RCREG, how many bytes it can store? If I'm not wrong, the coming data will be read 1 byte at a time when the flag bit RCIF is set right? And also for the transmiting Tx, the register TXREG will only accept 1 byte at a time? Could you please make it clear? Thank you!
 

n9352527

Joined Oct 14, 2005
1,198
I don't think you need to synchronise the clock on serial communication using UART. You need to set the PIC to have the same baud rate, number of bits and parity settings. The datasheet will outline all of these clearly.
 

thatoneguy

Joined Feb 19, 2009
6,359
thanks thatoneguy and mik3
Could you please give me more details about "interrupts or port polling"? Thanks
For the register RCREG, how many bytes it can store? If I'm not wrong, the coming data will be read 1 byte at a time when the flag bit RCIF is set right? And also for the transmiting Tx, the register TXREG will only accept 1 byte at a time? Could you please make it clear? Thank you!
As stated, the datasheet covers this, but if you didn't understand it.

The interrupt will trigger when the receive buffer is full, the size of the buffer depends on how you set up the port.

The TXREG cannot accept more than one packet at a time, as there is no FIFO buffer.
 
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