This is one of questions our prof gave to students in recent years and im preparing myself for this exam. i understand that Q1 and Q2 with Q1l and Q2l are making a differential amplifier with active load. but what is Q5 ? is that a current source ? if so why its Gate voltage comes from N1.
also the output is connected to a Cmos inverter well in digital this makes sense but here what if input of Cmos inverter is not either zero or vdd but vdd/2 ? isnt it going to also amplify the output in that range making the amplifier non-linear ?

 

It is the basic principle of a differential amplifier to have a large resistor at the common path of the (connected) source nodes - or better (for a larger common mode rejection ratio) a transistor Q5 acting as a current source.
Regarding the transistors Q3 and Q4: This combination is known to operate in the analog (amplification) mode with a high gain.
However, it must be biased properly app. at half of the total supply voltage. In your circuit, this is accomplished for negative feedback only as for opamps).
Remember how a high-gain operational amplifier is biased with negative feedback.
Bevause Q3 and Q4 form an inverting anplifier, you must use the non-inv. terminal (Vin+) of the diff. amplifier for negative loop gain.

 

What is the open loop gain of second stage (CMOS inverter)?
is it (gm3or gm4)(ro3||ro4) ?