refer to the diagram above,assume /BL , BL, WL are precharged to VDD.M1 and M5 will turn on, my question is why /Q voltage will increase as stated in my textbook? Isn't NMOS a pull down transistor, pulling voltage down to zero, why /Q voltage will increase

 

This is a simple single-bit memory cell constructed of two back to back CMOS inverters. BL and BL' are forced to compliments by the complimentary behaviour of the two inverters; so where BL = BL' = Vdd there is a race condition on the Q and Q' voltages.

What essentially happens is that Vdd on the input of the left-hand inverter opens M1 and closes M2, which in the absence of M5 would make the voltage at Q' = 0. Because you have artificially forced BL' = Vdd, when the compliment BL is also at that voltage, you have created a ratioed logic path from Vdd (on BL') and ground through M5 and M1, i.e. you have a floating voltage (not true digital) on Q'. This is not a true operating condition for this circuit because in reality if BL = 1 (Vdd) then BL = 0 (0V) and vice versa.

In fact the circuit would correct this condition because of the relative strengths of M5 and M6 (one will be weaker than the other).

Dave

 

This is a simple single-bit memory cell constructed of two back to back CMOS inverters. BL and BL' are forced to compliments by the complimentary behaviour of the two inverters; so where BL = BL' = Vdd there is a race condition on the Q and Q' voltages.

What essentially happens is that Vdd on the input of the left-hand inverter opens M1 and closes M2, which in the absence of M5 would make the voltage at Q' = 0. Because you have artificially forced BL' = Vdd, when the compliment BL is also at that voltage, you have created a ratioed logic path from Vdd (on BL') and ground through M5 and M1, i.e. you have a floating voltage (not true digital) on Q'. This is not a true operating condition for this circuit because in reality if BL = 1 (Vdd) then BL = 0 (0V) and vice versa.

In fact the circuit would correct this condition because of the relative strengths of M5 and M6 (one will be weaker than the other).

Dave

Thanks Dave.

let me clarify something.

1)/Q will increase to a floating voltage as you said initially when Artificially forced /BL to VDD,but it will decrease later?

2) the relative strength of M5 and M6 will determine the value of the floating voltage?and the voltage must not be high enough to drive the voltage on the right hand side of the inverter to avoid FLIP?

3)My last question,what will happen to /Q in the end, it will pull down to certain voltage after the initial increase in voltage?Am I correct on this.

Really thanks you very much.

 

Ok, firstly apologies for some of the details in my previous reply, my presumptions where on resulting steady-state conditions (and erroneously in isolation) that do not give much in the way of information to accurately answer your question. Furthermore, because this cell is a memory device, this cell needs to be considered for both read and write operations; what I said above applies only to write ops. Lastly, this is not just a single-bit memory cell, but is more accurately described as a SRAM single-bit memory cell (it will hold the value in the absence of recharging).

I think it best if I describe how this circuit works from the basics, therefore you will have a thorough appreciation of this circuit works.

Consider the circuit where WL = 0 which means M5 and M6 are off. The back-to-back inverters (lets call the first inverter INV1 [constructed from M1 and M2] and the second inverter INV2 [constructed from M3 and M4]) are isolated from the outside circuit. The input to INV1 is connected to the output of INV2 (Q) and the input to INV2 is connected to the output of INV1 (Q'). Since these are essentially cyclic-cascaded inverters Q and Q' will always be opposite values - cascaded inverters follow the output sequence 1-0-1-0-1-0...

By definition we say that the cell is storing a value of 1 when Q = Vdd and Q' = 0. Conversely the cell is storing a value of 0 when Q = 0 and Q' = Vdd. When isolated from external circuitry as described above, these are the only voltage levels that can exist on Q and Q'.

So what happens when we wish to perform a read or write operation from the memory cell, and how does that influence the voltage levels at Q and Q'?

Lets start with the read operation and consider the cell is storing a value 1 (i.e. Q = Vdd and Q' = 0).

With the read operation there is no way to know from outside of the cell what the value is, therefore we precharge the bit-lines BL and BL' to an equal intermediate voltage, say Vdd/2 (for the read operation this is a valid thing to do).

When we want to read the cell we set the WL line to Vdd, this switches on M5 and M6. BL' is pulled down to ground through M5 and M1, and BL is pulled up to Vdd through M4 and M6.

How does this affect the voltages at Q and Q'? The BL and BL' lines are capacitively loaded (in reality they would have a sense amplifier at the bottom to pull the value of BL and BL' to strong complimentary values, but in the interests of simplicity we shall omit this detail as your diagram has done). Since the BL and BL' line is capacitively loaded what we get are series RC-circuits (the transistors are the R and the bit-lines load contributes to the C). So at the point WL goes to Vdd we get an RC-response from an initial precharged value of Vdd/2 to either 0 or Vdd depending on whether the cell is storing a value 1 or 0.

See the attachment.

I goes without saying that the exact same thing will happen as above except with Vdd and 0 switched if we were reading a value of 0.

What about the write operation?

Lets assume the cell is storing the value 1 (i.e. Q = Vdd and Q' = 0) and we wish to write 0 to the cell. We would now need to force the value of BL and BL' to the required complementary values, which for writing a value of 0 would be BL = 0 and BL = Vdd. These values are hard-forced - that is they remain unchanged as the dynamics in the cell circuitry alter. Put simply BL will remain at 0 and BL' will remain at Vdd as the value is written.

To write the value set WL to Vdd, this opens M5 and M6. The value at Q (Vdd) is not consistent with the value at BL (0) and the value at Q' (0) is not consistent with the value at BL' (Vdd). The voltage at Q begins to discharge down towards 0 and the voltage at Q' begins to charge up to Vdd - again this is a series RC-circuit where there is parasitic capacitance at Q and Q'.

At a certain voltage (designed to be around Vdd/2) Q which is common to the input of INV1 will switch off M1 and switch on M2, this forcefully pulls Q' up to Vdd through M2. At the same time, Vdd on Q' is common to the input of INV2 which switches off M4 and switches on M3, this forcefully pulls Q down to ground. The value 0 is written to the cell.

Therefore you can see that the act of writing a value to the cell has the effect of switching the voltage at Q and Q' from 0 to Vdd and vice versa depending on what value was on the cell and what is being written to it. If the value being written to the cell is the same as the value on it then the voltages at Q and Q' do not change.

Hopefully, that gives you some details about how this circuit behaves and how the voltages on Q and Q' behave under the read and write operations. Does that make it any clearer?

Dave

 

Can I correct an error in my attachment - it is BL and BL' (and not Q and Q' as stated) that is pulled to Vdd or ground via Q and Q'. This is because the capacitance is on the bit-line.

Dave