Hello Friends,
I'm taking an electronics course this semester and i got to do a small homework project like for this course..
the amplifier is a differential input single ended cmos op amp
it has to meet the following specs as in the figure
I should use a positive +VDD/2 supply and a negative VDD/2 supply only.
The requirement to have VOS = 0 V means that there should be no differential mode offset; for a 0 V differential input and a common-mode input at the midpoint of the common-mode input range, the output should be 0 V under nominal supply conditions.
I am free to choose the midpoint of the common mode input range.
The available components are: NMOS transistors, PMOS transistors and resistors. Ideal sources can only be used to generate the supply voltages, not to generate bias currents.
Device Models
The device models are encapsulated in a sub-circuit; use:
x1 d g s b nmos w=10u l=0.13u
x2 d g s b pmos w=10u l=0.13u
The sub-circuit definitions are as follows:
.subckt nmos d g s b params: w=10u l=0.13u
m0 d g s b nmos_internal w={w} l={l}
.model nmos_internal
+ nmos level=1 kp=500u vto=0.3 gamma=0.2 phi=0.6
+ ld=0.025u
+ lambda={0.2*exp(0.13u/{l})/exp(1)}
.ends
.subckt pmos d g s b params: w=10u l=0.13u
m0 d g s b pmos_internal w={w} l={l}
.model pmos_internal
+ pmos level=1 kp=120u vto=-0.3 gamma=0.2 phi=0.6
+ ld=0.025u
+ lambda={0.15*exp(0.13u/{l})/exp(1)}
.ends
------------
i'm finding this very difficult to achieve
i tried something on a draft and is as follows:
am i close to something ??? any suggestions ?? how to assign a value for every transistor ?
how to complete the schematic ?? and examples close to what i'm going to do
thank you in advance
I'm taking an electronics course this semester and i got to do a small homework project like for this course..
the amplifier is a differential input single ended cmos op amp
it has to meet the following specs as in the figure
I should use a positive +VDD/2 supply and a negative VDD/2 supply only.
The requirement to have VOS = 0 V means that there should be no differential mode offset; for a 0 V differential input and a common-mode input at the midpoint of the common-mode input range, the output should be 0 V under nominal supply conditions.
I am free to choose the midpoint of the common mode input range.
The available components are: NMOS transistors, PMOS transistors and resistors. Ideal sources can only be used to generate the supply voltages, not to generate bias currents.
Device Models
The device models are encapsulated in a sub-circuit; use:
x1 d g s b nmos w=10u l=0.13u
x2 d g s b pmos w=10u l=0.13u
The sub-circuit definitions are as follows:
.subckt nmos d g s b params: w=10u l=0.13u
m0 d g s b nmos_internal w={w} l={l}
.model nmos_internal
+ nmos level=1 kp=500u vto=0.3 gamma=0.2 phi=0.6
+ ld=0.025u
+ lambda={0.2*exp(0.13u/{l})/exp(1)}
.ends
.subckt pmos d g s b params: w=10u l=0.13u
m0 d g s b pmos_internal w={w} l={l}
.model pmos_internal
+ pmos level=1 kp=120u vto=-0.3 gamma=0.2 phi=0.6
+ ld=0.025u
+ lambda={0.15*exp(0.13u/{l})/exp(1)}
.ends
------------
i'm finding this very difficult to achieve
i tried something on a draft and is as follows:
am i close to something ??? any suggestions ?? how to assign a value for every transistor ?
how to complete the schematic ?? and examples close to what i'm going to do
thank you in advance