# CMOS logic gate

#### m_dic

Joined Nov 8, 2005
2
hey cud someone pls help me with this

the question is :

sketch a transistor level schematic for a single stage CMOS logic gate for the following functions

Y= (ABC+D)'

Y=(AB + (C.(A+B ) ) ) '

i want to know how to connect the pmos and cmos gates in the pullup and pull down networks.

hope someone helps me soon.

#### stillme

Joined Oct 10, 2005
6

#### stillme

Joined Oct 10, 2005
6

#### Dave

Joined Nov 17, 2003
6,970
Originally posted by m_dic@Nov 8 2005, 10:47 PM
hey cud someone pls help me with this

the question is :

sketch a transistor level schematic for a single stage CMOS logic gate for the following functions

Y= (ABC+D)'

Y=(AB + (C.(A+B ) ) ) '

i want to know how to connect the pmos and cmos gates in the pullup and pull down networks.

hope someone helps me soon.
[post=11538]Quoted post[/post]​
Does the (') mean inverted (not), i.e. Y=NOT[(AB + (C.(A+B ) ) ) ]?

#### Dcrunkilton

Joined Jul 31, 2004
422
Originally posted by Dave@Nov 11 2005, 12:57 PM
Does the (') mean inverted (not), i.e. Y=NOT[(AB + (C.(A+B ) ) ) ]?
[post=11600]Quoted post[/post]​

You are correct the ' means NOT. It is hard to typeset the overbar, So, it is common to use the single quite mark to indicate inversion.

Unrelaed to this question about Invesion COMOS Gates at this web site has some info

#### Dave

Joined Nov 17, 2003
6,970
Ok, attached is the answer to the first one Y = (ABC + D)'

The key to deriving the CMOS layout is to try and look at the logic function, and to implement it with the nMOS transistors. When you have derived the nMOS layout, derive the pMOS layout by inverting every transistor position, i.e. when two transistor are in parallel in the nMOS layout put them in series in the pMOS layout.

Try this technique with the other function and post your answers to let us check if you like.

If you see anything wrong with my answer for the first layout, let me know.