CMOS logic gate

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m_dic

Joined Nov 8, 2005
2
hey cud someone pls help me with this

the question is :

sketch a transistor level schematic for a single stage CMOS logic gate for the following functions

Y= (ABC+D)'

Y=(AB + (C.(A+B)))'

i want to know how to connect the pmos and cmos gates in the pullup and pull down networks.

hope someone helps me soon.
 
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