# CMOS Inverter Electronics Question

Discussion in 'Homework Help' started by jegues, Nov 29, 2011.

1. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
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I'm having trouble with this question. (See figure attached)

How do I go about showing that the expression provided is indeed the maximum current that the inverter can sink under the mentioned constraints?

After I figure that part out I will make an attempt at the second portion of the question.

Thanks again!

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2. ### thatoneguy AAC Fanatic!

Feb 19, 2009
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I don't see any work from you, only scans from a bookk?

3. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
732
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$i_{dmax} = 0.075kn'(\frac{W}{L})_{n}V_{DD}^{2}$

$V_{OL} = 0.1V_{DD}$

To be honest with you, I don't have a good enough feel of where to start to give any reasonable attempt.

Can you give me a shove in the right direction?

I have no problems with making attempts at the solution as long as I have something to work from.

4. ### thatoneguy AAC Fanatic!

Feb 19, 2009
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I believe you are to work the given answer backwards from the end where it is stated that $k^'_n=\frac{115\mu A}{V^2} @V_{DD}=2.5V$

Make a simultaneous equation to find $(\frac{W}{L})_n$ while current is 7.5mA

Since, as I read it, the technology at $0.2V_{DD}$ allows 7.5mA with that same $k'_n$

That's my shot in the dark, it's been a while since college, and there are several statements intermixed with questions in that little paragraph they show.

Are the terms or methods of deriving $K'_n$ and $\frac{W}{L}$ defined somewhere on that same page outside of this question?

5. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
732
45
Before making equations for W/L I need to show how the equation they've given me comes to be.

That's what I'm trying to figure out before I crunch out W/L.

6. ### thatoneguy AAC Fanatic!

Feb 19, 2009
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I thought (hoped?) that would have been covered in the book or in class.

I guess we need to wait for t_n_k to arrive.

7. ### t_n_k AAC Fanatic!

Mar 6, 2009
5,448
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Use the general relationship

$I_D=\frac{K'W}{L}$(V_{GS}-V_T)V_{DS} -\frac{V_{DS}^2}{2}$$

For the NMOS on state ...

Substitute

$V_{GS}=V_{DD}, \ V_T=0.2V_{DD}\ & \ V_{DS} =0.1V_{DD}$

and you should obtain the required relationship.