Hello,

I'm currently working on my Final Year Project for university and have read that to ensure stable operation all unused logic inputs should be tied to either +V or 0V when using CMOS.

There however doesn't seem to be clarification as to whether this means unused inputs on a currently in use function on not. What I mean by this is, for example, a 4013 dual D type flip flop... if I am using only one of them, should I tye all the inputs of the other to 0V or does it just mean tying set and reset for example on the flip flop I'm using?

I have scoured all over the net and in many reference books but not found a clear answer. My technician at university says it only applies to the flip-flop or logic gate in use and not other functions in the same IC.

Any clarification would be appreciated and if anyone has a reference source too that would be fab, but don't worry if not!

Also another quick question, does CMOS stand for Complimentary Metal Oxide Semiconductor or Silicon? I have read both in different texts, although I thought it was semiconductor initially?

 

Your technician is wrong. You should tie ALL unused inputs to VCC or GND. The reason for this is to prevent the unused part from oscillating, which increases power consumption and may effect the operation of any circuit in proximity to the unused part, via crosstalk or other coupling mechanisms.

The 'S' in CMOS stands for Semiconductor, just like the 'S' in NMOS, PMOS and well just plain MOS.

 

Thanks for the clarification. I thought it was Semiconductor and I read in the introduction to CMOS Cookbook by Don Lancaster Silicon. When searching the net too, it came up with both results!

 

The better way is to connecting all the inputs to GND, you can't connecting anyone of set or reset to Hi, unless you want to preset a status to the output, D connecting to GND can be avoid transfer a Hi to Q output, ck connecting to GND to prevent occur a pulse to enable when D connected to Hi, and it will output a Hi on Q.

 

I'll second what Brownout said.

Having been published in 1977, I'm sure the acronym has evolved, or at least has been better defined, since your book was new.

You can make CMOS devices from semiconductors other than silicon.

 

To understand why all inputs need to be tied, note that the CMOS input is a very high impedance and thus the voltage of an unconnected input can float to an arbitrary level, depending upon the various leakage currents in the circuit. Thus the circuit may generate strange outputs and be sensitive to the proximity of other objects such as your hand. Also if the input floats to a voltage half-way between a logic 0 and 1, both the associated N and P MOSFET transistors with that input may conduct at the same time, causing higher circuit current and power dissipation.

 

The better way is to connecting all the inputs to GND, you can't connecting anyone of set or reset to Hi, unless you want to preset a status to the output, D connecting to GND can be avoid transfer a Hi to Q output, ck connecting to GND to prevent occur a pulse to enable when D connected to Hi, and it will output a Hi on Q.

You can connect inputs of an unused device to either Vcc or GND. If the device is unused it doesn't matter in the slightest which one you choose. In layout you might actually have a reason to have an unrestricted choice.

 

I'll second what Brownout said.

Having been published in 1977, I'm sure the acronym has evolved, or at least has been better defined, since your book was new.

You can make CMOS devices from semiconductors other than silicon.

My National CMOS book from 1972 unequivocally uses 'Semiconductor'

 

My National CMOS book from 1972 unequivocally uses 'Semiconductor'

So, sounds like the latter option.

Either way, the acronym is incorrect (or at partially misinformed)/misused as not all the devices we call MOSFETs, or MOS devices in general, use oxide as an insulating later.

 

So, sounds like the latter option.

Either way, the acronym is incorrect (or at partially misinformed)/misused as not all the devices we call MOSFETs, or MOS devices in general, use oxide as an insulating later.

The more generic term MISFETs is often used for those that don't use oxide (Metal Insulating Field Effect Transistor).

 

The more generic term MISFETs is often used for those that don't use oxide (Metal Insulating Field Effect Transistor).

Sounds like a misfit MOSFET.

I usually call them Insulated Gate Field Effect Transistors(IGFETs), in case we ever stop using metal for the contacts.

 

You can connect inputs of an unused device to either Vcc or GND. If the device is unused it doesn't matter in the slightest which one you choose. In layout you might actually have a reason to have an unrestricted choice.

You have to check the set and reset of CD4013.

If you connecting the set pin to Hi(vcc) then the Q will be always output a Hi(1), If you connecting the reset pin to Hi(vcc) then the Q will be always output a Low(0), and above two kinds of situations has priority then D and ck, and never affected by the D and ck.

 

You have to check the set and reset of CD4013.

If you connecting the set pin to Hi(vcc) then the Q will be always output a Hi(1), If you connecting the reset pin to Hi(vcc) then the Q will be always output a Low(0), and above two kinds of situations has priority then D and ck, and never affected by the D and ck.

I know that. The package contains two(2) flip-flops. If I use one of the two then I need to connect each of the inputs in a practical and meaningful way. If the other one is unused then I can connect it's inputs in an arbitrary way so long as each input is connected to a valid logic level, either high(Vcc) or low(GND). Certainly you agree with this -- right?

 

I know that. The package contains two(2) flip-flops. If I use one of the two then I need to connect each of the inputs in a practical and meaningful way. If the other one is unused then I can connect it's inputs in an arbitrary way so long as each input is connected to a valid logic level, either high(Vcc) or low(GND). Certainly you agree with this -- right?

No.
For a CD4013, whatever the set or reset, if you don't want to use it, it should be connecting to GND, you can't connecting to Vcc or a high logic, for a 74LS74, it has the contrary situation.

To avoid a situation as:
D and ck connecting to Vcc(high), when the power up, it has a chance to transfer a high from D to Q, so when the D and Q are unused, they better connecting to GND.

 

No.
For a CD4013, whatever the set or reset, if you don't want to use it, it should be connecting to GND, you can't connecting to Vcc or a high logic, for a 74LS74, it has the contrary situation.

To avoid a situation as:
D and ck connecting to Vcc(high), when the power up, it has a chance to transfer a high from D to Q, so when the D and Q are unused, they better connecting to GND.

Q is an output and shouldn't be connected to anything. S and R can safely be connected to Vcc, just look at the truth table - there is even a condition for it.

While ground is probably the better option for these specific inputs, the point of tying the inputs to a logic level is to prevent oscillation; this is accomplished with either input logic level.

 

Q is an output and shouldn't be connected to anything. S and R can safely be connected to Vcc, just look at the truth table - there is even a condition for it.

Sorry, about the Q that it was a typing mistake, it is ck.
I know the conditions of R and S, that just using when the D and ck unused, but the situation here is unused pins, so what you saying is assuming that if you want to set the output on a logic level for some situations, and I used that function sometimes.

While ground is probably the better option for these specific inputs, the point of tying the inputs to a logic level is to prevent oscillation; this is accomplished with either input logic level.

Most of situations just like you said, but when we using CD4013 or 74LS74, we have to treat them like two groups, one is for D and ck, another is for set and reset, when we connecting set and reset should be carefully, but as your knowledage is not a problem.

Another problem could be occur, that is during the power up, the Q will became a High output not a normal Low, specially when the interference is happening.

 

[...]
Another problem could be occur, that is during the power up, the Q will became a High output not a normal Low, specially when the interference is happening.

Since we are taking about CMOS devices, it doesn't matter which state the output ends up in, so long as it stays there - the power dissipation is the same for both...