Clock Pulses

Thread Starter

Kittu20

Joined Oct 12, 2022
431
In summary, during the Read operation in I2C communication:

The slave device takes control of the SDA line to send data to the master.
The master receives each bit of data from the slave while the SCL line is held high.
This data reception is similar in concept to the write operation, where the master controls the SDA line to send data to the slave.

In I2C, the clock signal (SCL) is typically generated by the master device. I don't understand how slave takes control of clock?
 

drjohsmith

Joined Dec 13, 2021
850
I wanted to share my understanding of the data transmission process for I2C . I'm hoping to get your insights and corrections to ensure that I have a clear grasp of the concept. I believe this could be beneficial for others who are also exploring I2C. So, without further ado, here are the steps as I understand them:

I2C Data Transmission : Address and Data

Step 1: Start Condition
To start communication on the I2C bus, we start with a Start Condition:

  • Set the SDA line to a logic low level.
  • Keep the SCL line high.

Step 2: Address and Data Transmission
Next, we transmit the Slave Address and indicate whether we want to Read or Write data:

  • Transmit the Slave Address (7 bits), which for this example is 1001010.
  • Include the Read/Write (R/W) Bit, where 0 signifies a Write operation.
  • Await an Acknowledgment (ACK) from the addressed slave to confirm its presence.

Understanding the Data Validity and Change:

  • Data is considered valid when the SCL line is high.
  • Data changes should occur when the SCL line is low.
  • Stable data is indicated by the rising edge of the SCL signal.

Step 3 : 8-Bit Transfer for Address : example is 1001010.

For each bit of the 7-bit Slave Address:

  • When the SCL line is low, set the SDA line according to the bit being transmitted.
  • Bit 1 (MSB): Set SDA high while SCL is low (Transmit 1).
  • Bit 2: Set SDA low while SCL is low (Transmit 0).
  • Bit 3: Set SDA low while SCL is low (Transmit 0).
  • Bit 4: Set SDA high while SCL is low (Transmit 1).
  • Bit 5: Set SDA low while SCL is low (Transmit 0).
  • Bit 6: Set SDA high while SCL is low (Transmit 1).
  • Bit 7: Set SDA low while SCL is low (Transmit 0).

Step 4: Acknowledge (ACK) and Not Acknowledge (NACK)
After sending the Slave Address, await an Acknowledgment (ACK) or Not Acknowledge (NACK):

  • The slave device sends an ACK if the address was successfully received.

Step 5: 8-Bit Transfer for Data : For example 10101010

  • For each bit sent, master sets SDA line while SCL is low
  • Bit 1 (MSB): Set SDA to high while SCL is low (Transmit 1)
  • Bit 2: Set SDA to low while SCL is low (Transmit 0)
  • Bit 3: Set SDA to high while SCL is low (Transmit 1)
  • Bit 4: Set SDA to low while SCL is low (Transmit 0)
  • Bit 5: Set SDA to high while SCL is low (Transmit 1)
  • Bit 6: Set SDA to low while SCL is low (Transmit 0)
  • Bit 7: Set SDA to high while SCL is low (Transmit 1)
  • Bit 8 (LSB): Set SDA to low while SCL is low (Transmit 0)
  • SDA state changes according to the data while SCL is low
  • SCL transitions high to signal data readiness

Step 7: Acknowledge (ACK) and Not Acknowledge (NACK)
Again, await an Acknowledgment (ACK) or Not Acknowledge (NACK):

  • The slave device sends an ACK if the data was successfully received.

Step 8: Stop Condition
To stop the transmission, we send a Stop Condition:

  • Set the SDA line high while SCL is high.
Sounds like you have it.
I'm on move sou only quick read but sounds like you have it.
Mostly of these things you will find are covered by pre available libraries and parts , but it's good to have the basics of heart
 

drjohsmith

Joined Dec 13, 2021
850
In summary, during the Read operation in I2C communication:

The slave device takes control of the SDA line to send data to the master.
The master receives each bit of data from the slave while the SCL line is held high.
This data reception is similar in concept to the write operation, where the master controls the SDA line to send data to the slave.

In I2C, the clock signal (SCL) is typically generated by the master device. I don't understand how slave takes control of clock?
The slave can take control of the clock , clock stretching .
Remember the bus is only driven low , and pulled high.
If the slave wants the clock slower , once clock has gone low fromaster, slave can hold clock low . Master will not move to next state till clock is high , I've slave has released it
 

WBahn

Joined Mar 31, 2012
29,867
In summary, during the Read operation in I2C communication:

The slave device takes control of the SDA line to send data to the master.
The master receives each bit of data from the slave while the SCL line is held high.
This data reception is similar in concept to the write operation, where the master controls the SDA line to send data to the slave.

In I2C, the clock signal (SCL) is typically generated by the master device. I don't understand how slave takes control of clock?
It sounds like you still don't understand that the SDA and SCL lines in I2C are wired-AND. They are passively pulled HI and any device on the bus can actively pull them LO at any time. The controller (or controllers, if there's more than one) are required to examine the state of the line whenever they write a 1 to the line (which releases the line with the expectation that the the passive pullup will bring the line to a HI state). If the line remains LO, then the controller knows that some other device is actively pulling it LO. Depending on whether it is the SDA or the SCL line is is involved and what phase of communication they are in, the controller then either has to surrender the bus and let the other controller (the one that is actively driving the line LO) take over, or pause the communication until the target device releases the clock line.
 

Thread Starter

Kittu20

Joined Oct 12, 2022
431
It sounds like you still don't understand that the SDA and SCL lines in I2C are wired-AND.
I'm currently in the process of learning about I2C communication and I'm trying to understand concept of bit-banging for data transmission to an I2C device. I've written a code that implements bit-banging for I2C communication to send data to an I2C device. I wanted to share my code here and get some insights and feedback on whether my approach makes sense and whether there are any improvements or suggestions you might have.

C:
#include <stdio.h>
#include <stdint.h>

// Define I2C pins
#define SDA   4 // SDA pin number
#define SCL   5 // SCL pin number

// Define logic levels for microcontroller
#define HIGH  1
#define LOW   0

// Define ACK and NACK values
#define ACK   0
#define NACK  1

// delay function
void delay() {
    // Implement a delay (e.g., using loops)
}

// I2C Ideal Communication
void i2c_ideal() {
    // In ideal condition, no device is actively driving the I2C bus.
    // Pull-up resistors maintain a logical high level at the SDA and SCL pins.
    SDA = HIGH;
    SCL = LOW;
}

// I2C Start Condition
void i2c_start() {
    SDA = LOW;    // SDA line is set to logic low to initiate start condition
    delay();     
    SCL = LOW;    // Transition SCL to low to complete the start condition
}

// I2C Transfer Bit
void i2c_transfer_bit(uint8_t bit) {
    SDA = bit;     // Set SDA to transfer the bit (0 or 1)
    SCL = HIGH;    // Generate a clock pulse
    delay();       // Wait for a brief period to ensure proper signaling
    SCL = LOW;     // Transition SCL to low to complete the clock pulse
}

// I2C Stop Condition
void i2c_stop() {
    SDA = LOW;     // SDA line is set to logic low to initiate stop condition
    SCL = HIGH;    // Generate a clock pulse while keeping SDA low
    delay();       
    SDA = HIGH;    // Release SDA to complete stop
}

// I2C Check ACK/NACK
uint8_t i2c_check_ack() {
    SDA = HIGH;    // Set SDA as input to read ACK/NACK
    SCL = HIGH;    // Generate a clock pulse
    delay();       // Wait for a brief period to ensure proper signaling
    uint8_t ack_nack = SDA; // Read the value of SDA line to determine ACK/NACK
    SCL = LOW;     // Transition SCL to low after clock pulse
    delay();       // Delay after transitioning SCL to low
    return (ack_nack == ACK) ? ACK : NACK;
}

int main() {
    // Initialize I2C pins and ideal communication
    i2c_ideal();
    
    // Example: Transfer a single byte
    uint8_t data_byte = 0xAB; //  data we want to send
    
    i2c_start();

    // Transmitting bits in I2C communication requires sending the least significant bit (LSB) first.
    // Therefore, we use a reversed loop to transmit each bit from the most significant bit (MSB) to LSB.
    for (int i = 7; i >= 0; i--) {
        uint8_t bit_to_send = (data_byte >> i) & 1; // Extract the bit to send at position i
        i2c_transfer_bit(bit_to_send);
    }
    
    uint8_t ack_nack = i2c_check_ack(); // Check ACK/NACK response

    if (ack_nack == NACK) {
        // Handle NACK: The slave did not acknowledge the data, indicating an error
        printf("NACK received. Data not accepted by the slave.\n");
        
    } else {
        // Handle ACK: The slave acknowledged the data successfully
        printf("ACK received. Data accepted by the slave.\n");

    }

    i2c_stop(); // Generate a stop condition
    
    return 0;
}
 

MrAl

Joined Jun 17, 2014
11,272
From what I understand:

SCL Pulled Low by the Master: The master device initiates the clock pulses by actively driving the SCL line low. This means the master briefly connects the SCL line to ground (GND) to create a low logic level (Logic 0) on the line.

Pull-Up Resistor Pulls SCL High: When the master releases the SCL line, the pull-up resistor connected to the SCL line ensures that the line is pulled back to a high logic level (Logic 1). The pull-up resistor provides a path for current to flow from the supply voltage (Vcc) to the SCL line.

Creating Clock Pulses: The process of the master pulling the SCL line low and then the pull-up resistor pulling it high creates a clock pulse. Each clock pulse indicates a timing interval,

Does master write bit at leading edge and slave read bit at falling edge of clock signal ?
Hi,

It may take a little time to understand this protocol.
See if this helps...
 

Attachments

drjohsmith

Joined Dec 13, 2021
850
I'm currently in the process of learning about I2C communication and I'm trying to understand concept of bit-banging for data transmission to an I2C device. I've written a code that implements bit-banging for I2C communication to send data to an I2C device. I wanted to share my code here and get some insights and feedback on whether my approach makes sense and whether there are any improvements or suggestions you might have.

C:
#include <stdio.h>
#include <stdint.h>

// Define I2C pins
#define SDA   4 // SDA pin number
#define SCL   5 // SCL pin number

// Define logic levels for microcontroller
#define HIGH  1
#define LOW   0

// Define ACK and NACK values
#define ACK   0
#define NACK  1

// delay function
void delay() {
    // Implement a delay (e.g., using loops)
}

// I2C Ideal Communication
void i2c_ideal() {
    // In ideal condition, no device is actively driving the I2C bus.
    // Pull-up resistors maintain a logical high level at the SDA and SCL pins.
    SDA = HIGH;
    SCL = LOW;
}

// I2C Start Condition
void i2c_start() {
    SDA = LOW;    // SDA line is set to logic low to initiate start condition
    delay();    
    SCL = LOW;    // Transition SCL to low to complete the start condition
}

// I2C Transfer Bit
void i2c_transfer_bit(uint8_t bit) {
    SDA = bit;     // Set SDA to transfer the bit (0 or 1)
    SCL = HIGH;    // Generate a clock pulse
    delay();       // Wait for a brief period to ensure proper signaling
    SCL = LOW;     // Transition SCL to low to complete the clock pulse
}

// I2C Stop Condition
void i2c_stop() {
    SDA = LOW;     // SDA line is set to logic low to initiate stop condition
    SCL = HIGH;    // Generate a clock pulse while keeping SDA low
    delay();      
    SDA = HIGH;    // Release SDA to complete stop
}

// I2C Check ACK/NACK
uint8_t i2c_check_ack() {
    SDA = HIGH;    // Set SDA as input to read ACK/NACK
    SCL = HIGH;    // Generate a clock pulse
    delay();       // Wait for a brief period to ensure proper signaling
    uint8_t ack_nack = SDA; // Read the value of SDA line to determine ACK/NACK
    SCL = LOW;     // Transition SCL to low after clock pulse
    delay();       // Delay after transitioning SCL to low
    return (ack_nack == ACK) ? ACK : NACK;
}

int main() {
    // Initialize I2C pins and ideal communication
    i2c_ideal();
   
    // Example: Transfer a single byte
    uint8_t data_byte = 0xAB; //  data we want to send
   
    i2c_start();

    // Transmitting bits in I2C communication requires sending the least significant bit (LSB) first.
    // Therefore, we use a reversed loop to transmit each bit from the most significant bit (MSB) to LSB.
    for (int i = 7; i >= 0; i--) {
        uint8_t bit_to_send = (data_byte >> i) & 1; // Extract the bit to send at position i
        i2c_transfer_bit(bit_to_send);
    }
   
    uint8_t ack_nack = i2c_check_ack(); // Check ACK/NACK response

    if (ack_nack == NACK) {
        // Handle NACK: The slave did not acknowledge the data, indicating an error
        printf("NACK received. Data not accepted by the slave.\n");
       
    } else {
        // Handle ACK: The slave acknowledged the data successfully
        printf("ACK received. Data accepted by the slave.\n");

    }

    i2c_stop(); // Generate a stop condition
   
    return 0;
}
though I admire you for wanting to write the code, and doubly so for wanting to share,
just be aware that there are 1001 pre existing , proven packages out there to do I2C bit bnging,
even if you dont want to use them ,
a suggestion, get somethign like an arduino ( I like the teenssey form PJR ) ,
not only does it give you an insight as to how I2C works, but you can use the teensey to be a @slave@ that prints ot the screen what ots doing, so you cna use it to debug you I2C master with a known working module.
 

MrChips

Joined Oct 2, 2009
30,497
I can see two mistakes.
SDA and SCL are open collector or open drain outputs.

The idle condition of SDA and SCL are both disabled, open drain.
 

Thread Starter

Kittu20

Joined Oct 12, 2022
431
I can see two mistakes.
SDA and SCL are open collector or open drain outputs.

The idle condition of SDA and SCL are both disabled, open drain.
You are correct. SDA and SCL are open-drain outputs in I2C communication. code now initializes the SDA and SCL lines correctly, Here's the corrected code with the proper comments
C:
#include <stdio.h>
#include <stdint.h>

// Define I2C pins
#define SDA   4 // SDA pin number
#define SCL   5 // SCL pin number

// Define logic levels for microcontroller
#define HIGH  1
#define LOW   0

// Define ACK and NACK values
#define ACK   0
#define NACK  1

// delay function
void delay() {
    // Implement a delay (e.g., using loops)
}

// I2C Ideal Communication
void i2c_ideal() {
    // In ideal condition, no device is actively driving the I2C bus.
    // Pull-up resistors maintain a logical high level at the SDA and SCL pins.
    SDA = HIGH;
    SCL = HIGH; // SCL is also high in idle condition (corrected)
}

// I2C Start Condition
void i2c_start() {
    SDA = LOW;    // SDA line is set to logic low to initiate start condition
    delay();    
    SCL = LOW;    // Transition SCL to low to complete the start condition
}

// I2C Transfer Bit
void i2c_transfer_bit(uint8_t bit) {
    SDA = bit;     // Set SDA to transfer the bit (0 or 1)
    SCL = HIGH;    // Generate a clock pulse
    delay();       // Wait for a brief period to ensure proper signaling
    SCL = LOW;     // Transition SCL to low to complete the clock pulse
}

// I2C Stop Condition
void i2c_stop() {
    SDA = LOW;     // SDA line is set to logic low to initiate stop condition
    SCL = HIGH;    // Generate a clock pulse while keeping SDA low
    delay();      
    SDA = HIGH;    // Release SDA to complete stop
}

// I2C Check ACK/NACK
uint8_t i2c_check_ack() {
    SDA = HIGH;    // Set SDA as input to read ACK/NACK
    SCL = HIGH;    // Generate a clock pulse
    delay();       // Wait for a brief period to ensure proper signaling
    uint8_t ack_nack = SDA; // Read the value of SDA line to determine ACK/NACK
    SCL = LOW;     // Transition SCL to low after clock pulse
    delay();       // Delay after transitioning SCL to low
    return (ack_nack == ACK) ? ACK : NACK;
}

int main() {
    // Initialize I2C pins and ideal communication
    i2c_ideal();
   
    // Example: Transfer a single byte
    uint8_t data_byte = 0xAB; //  data we want to send
   
    i2c_start();

    // Transmitting bits in I2C communication requires sending the least significant bit (LSB) first.
    // Therefore, we use a reversed loop to transmit each bit from the most significant bit (MSB) to LSB.
    for (int i = 7; i >= 0; i--) {
        uint8_t bit_to_send = (data_byte >> i) & 1; // Extract the bit to send at position i
        i2c_transfer_bit(bit_to_send);
    }
   
    uint8_t ack_nack = i2c_check_ack(); // Check ACK/NACK response

    if (ack_nack == NACK) {
        // Handle NACK: The slave did not acknowledge the data, indicating an error
        printf("NACK received. Data not accepted by the slave.\n");
       
    } else {
        // Handle ACK: The slave acknowledged the data successfully
        printf("ACK received. Data accepted by the slave.\n");

    }

    i2c_stop(); // Generate a stop condition
   
    return 0;
}
 

Thread Starter

Kittu20

Joined Oct 12, 2022
431
Hi,

It may take a little time to understand this protocol.
See if this helps...
I am shareing a visual representation I created that I found quite helpful in understanding I2C communication and its signaling details. I've added annotations to indicate key points in the signal waveform, which I believe could be beneficial for others who are learning or trying to grasp the concept. In the image, you'll notice that I've highlighted the rising and falling edges of the clock signal (SCL) using an up arrow and down arrow, respectively. Additionally, I've included a representation of the seven bits of the slave address along with their corresponding logic values.

1691844750064.png
 

drjohsmith

Joined Dec 13, 2021
850
You are correct. SDA and SCL are open-drain outputs in I2C communication. code now initializes the SDA and SCL lines correctly, Here's the corrected code with the proper comments
C:
#include <stdio.h>
#include <stdint.h>

// Define I2C pins
#define SDA   4 // SDA pin number
#define SCL   5 // SCL pin number

// Define logic levels for microcontroller
#define HIGH  1
#define LOW   0

// Define ACK and NACK values
#define ACK   0
#define NACK  1

// delay function
void delay() {
    // Implement a delay (e.g., using loops)
}

// I2C Ideal Communication
void i2c_ideal() {
    // In ideal condition, no device is actively driving the I2C bus.
    // Pull-up resistors maintain a logical high level at the SDA and SCL pins.
    SDA = HIGH;
    SCL = HIGH; // SCL is also high in idle condition (corrected)
}

// I2C Start Condition
void i2c_start() {
    SDA = LOW;    // SDA line is set to logic low to initiate start condition
    delay();   
    SCL = LOW;    // Transition SCL to low to complete the start condition
}

// I2C Transfer Bit
void i2c_transfer_bit(uint8_t bit) {
    SDA = bit;     // Set SDA to transfer the bit (0 or 1)
    SCL = HIGH;    // Generate a clock pulse
    delay();       // Wait for a brief period to ensure proper signaling
    SCL = LOW;     // Transition SCL to low to complete the clock pulse
}

// I2C Stop Condition
void i2c_stop() {
    SDA = LOW;     // SDA line is set to logic low to initiate stop condition
    SCL = HIGH;    // Generate a clock pulse while keeping SDA low
    delay();     
    SDA = HIGH;    // Release SDA to complete stop
}

// I2C Check ACK/NACK
uint8_t i2c_check_ack() {
    SDA = HIGH;    // Set SDA as input to read ACK/NACK
    SCL = HIGH;    // Generate a clock pulse
    delay();       // Wait for a brief period to ensure proper signaling
    uint8_t ack_nack = SDA; // Read the value of SDA line to determine ACK/NACK
    SCL = LOW;     // Transition SCL to low after clock pulse
    delay();       // Delay after transitioning SCL to low
    return (ack_nack == ACK) ? ACK : NACK;
}

int main() {
    // Initialize I2C pins and ideal communication
    i2c_ideal();
  
    // Example: Transfer a single byte
    uint8_t data_byte = 0xAB; //  data we want to send
  
    i2c_start();

    // Transmitting bits in I2C communication requires sending the least significant bit (LSB) first.
    // Therefore, we use a reversed loop to transmit each bit from the most significant bit (MSB) to LSB.
    for (int i = 7; i >= 0; i--) {
        uint8_t bit_to_send = (data_byte >> i) & 1; // Extract the bit to send at position i
        i2c_transfer_bit(bit_to_send);
    }
  
    uint8_t ack_nack = i2c_check_ack(); // Check ACK/NACK response

    if (ack_nack == NACK) {
        // Handle NACK: The slave did not acknowledge the data, indicating an error
        printf("NACK received. Data not accepted by the slave.\n");
      
    } else {
        // Handle ACK: The slave acknowledged the data successfully
        printf("ACK received. Data accepted by the slave.\n");

    }

    i2c_stop(); // Generate a stop condition
  
    return 0;
}
Practical point.
Your using the delay function.
Abs no problem with that for a test
But
In a real system , delay will stall the processor ,
In a real system you would be using interupts.
 

MrChips

Joined Oct 2, 2009
30,497
The graphics you have shown of SCL and SDA is for a data byte transmission, not the slave address.
The slave address is only 7 bits, followed by a R/W bit.

Here is an example oscilloscope screen capture of I2C transmission.

1691849839782.png
 

MrAl

Joined Jun 17, 2014
11,272
I am shareing a visual representation I created that I found quite helpful in understanding I2C communication and its signaling details. I've added annotations to indicate key points in the signal waveform, which I believe could be beneficial for others who are learning or trying to grasp the concept. In the image, you'll notice that I've highlighted the rising and falling edges of the clock signal (SCL) using an up arrow and down arrow, respectively. Additionally, I've included a representation of the seven bits of the slave address along with their corresponding logic values.

View attachment 300319
Hi,

Ok great.
There are also variations for what kind of device you are using such as ADC or EEPROM. They would have different word requirements.
If you do check out a I2C library you will find code that works and you could look that over and that should tell you a lot about this. When I did my first I2C code I didn't have that so I had to wing it and it took a while to figure everything out.
 

Thread Starter

Kittu20

Joined Oct 12, 2022
431
Hello everyone

I am stumbled upon an intriguing scenario. Imagine two master devices (Master A and Master B) writing data to a single slave. Later, Master A wants to read data from the same slave.

My question is: How does the slave know which master to send the requested data to, especially when both masters have interacted with it before? I understand I2C uses addressing and read/write bits, but I'm curious about the specifics.

How does the slave differentiate between Master A and Master B?

What about arbitration if both masters want to read simultaneously?
 

MrChips

Joined Oct 2, 2009
30,497
Hello everyone

I am stumbled upon an intriguing scenario. Imagine two master devices (Master A and Master B) writing data to a single slave. Later, Master A wants to read data from the same slave.

My question is: How does the slave know which master to send the requested data to, especially when both masters have interacted with it before? I understand I2C uses addressing and read/write bits, but I'm curious about the specifics.

How does the slave differentiate between Master A and Master B?

What about arbitration if both masters want to read simultaneously?
The slave does not initiate communications. It is the master that takes control of the bus and then sends a request for data from the slave.

This is why it is called Master/Slave communications.
 

drjohsmith

Joined Dec 13, 2021
850
Hello everyone

I am stumbled upon an intriguing scenario. Imagine two master devices (Master A and Master B) writing data to a single slave. Later, Master A wants to read data from the same slave.

My question is: How does the slave know which master to send the requested data to, especially when both masters have interacted with it before? I understand I2C uses addressing and read/write bits, but I'm curious about the specifics.

How does the slave differentiate between Master A and Master B?

What about arbitration if both masters want to read simultaneously?
There can only every be one I2C master at any one time, so this can never happen.
there is a mschanisum in the spec for masters to negotiate / avoid / cope with two masters wanting access,
 

WBahn

Joined Mar 31, 2012
29,867
Hello everyone

I am stumbled upon an intriguing scenario. Imagine two master devices (Master A and Master B) writing data to a single slave. Later, Master A wants to read data from the same slave.

My question is: How does the slave know which master to send the requested data to, especially when both masters have interacted with it before? I understand I2C uses addressing and read/write bits, but I'm curious about the specifics.

How does the slave differentiate between Master A and Master B?

What about arbitration if both masters want to read simultaneously?
You are asking questions that, in part, go beyond the I2C protocol and might be handles by a higher level protocol. The I2C protocol operates at a level of enabling individual messages to be passed from a controller to a target (master to a slave, but the protocol prefers the terms 'controller' and 'target'), it does not say what the payloads of the messages are.

A controller can request information from a target, but the controller controls the bus, so it will provide the clock signals (the target can stretch them, though).

In your question, the "later" is a key part of it. There are two options. First, Master A can again act as a controller and initiate a conversation with the target. But let's say that Master A doesn't know when the slave will have the information available. In that case, it could use a higher level protocol in which, in the first transaction, Master A tells it what information it wants and also provides its address. Then, later, once the slave has the information, it acts as a controller to initiate conversation with Master A (which now acts as a target).

As for arbitration when two controllers try to access the bus at the same time, that has already been answered several times in this thread. For instance:

"The possibility of connecting more than one microcontroller to the I2C-bus means that more than one controller could try to initiate a data transfer at the same time. To avoid the chaos that might ensue from such an event, an arbitration procedure has been developed. This procedure relies on the wired-AND connection of all I2C interfaces to the I 2C-bus. If two or more controllers try to put information onto the bus, the first to produce a ‘one’ when the other produces a ‘zero’ loses the arbitration. "

and

" It sounds like you still don't understand that the SDA and SCL lines in I2C are wired-AND. They are passively pulled HI and any device on the bus can actively pull them LO at any time. The controller (or controllers, if there's more than one) are required to examine the state of the line whenever they write a 1 to the line (which releases the line with the expectation that the the passive pullup will bring the line to a HI state). If the line remains LO, then the controller knows that some other device is actively pulling it LO. Depending on whether it is the SDA or the SCL line is is involved and what phase of communication they are in, the controller then either has to surrender the bus and let the other controller (the one that is actively driving the line LO) take over, or pause the communication until the target device releases the clock line. "
 
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