In that case a CD4013 (or similar) D-flipflop should fit the bill. A fast-rising positive-going edge on the Clk input will change the state if the D input is connected to the not-Q output.Alec_T, it will just toggle from one state to the next.
In that case a CD4013 (or similar) D-flipflop should fit the bill. A fast-rising positive-going edge on the Clk input will change the state if the D input is connected to the not-Q output.Alec_T, it will just toggle from one state to the next.
Synchronous and asynchronous refers to how the logic sequences............. I'm using the word, "clock", in the only way I know how to phrase it. As each section of the circuit finishes it's job the next flip flop will start the following sequence. In this project that "clock" signal is from a comparator reaching a certain voltage. This is why it is what I understand to be an asynchronous system. What else would it be called?
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"An asynchronous system has no clocks so the logic outputs simply follows the signal inputs delayed only by any circuit propagation delays."Synchronous and asynchronous refers to how the logic sequences.
An asynchronous system has no clocks so the logic outputs simply follows the signal inputs delayed only by any circuit propagation delays.
A synchronous signal performs the logic based upon the signals only when a clock occurs.
When the clock occurs has no bearing on whether the system is synchronous or asynchronous.
I'd diode-OR them right at the Clk pin. They both need to be fast-rising signals.How are two individual signals put on the "clock" pin.
It takes a bit of know-how and experience to be able to design with flip-flops comfortably.Next dumb question on this . How are two individual signals put on the "clock" pin. They are separate signals that will never be there at the same time. One toggles 'Q' high and the next one will toggle 'Q' low. Do I put them both on separate edge detectors then into an 'or' gate? Or use separate edge detectors and diode 'or them?
Thank you Alec, that was my first guess. But am wrong most of the time with electronics it seems. Just a small signal Schottky diode, correct?I'd diode-OR them right at the Clk pin. They both need to be fast-rising signals.
What you are talking about is known as a "gated clock" which, in most instances, is a really bad thing. In general, asynchronous designs are much harder to do correctly because they are much more sensitive to several issues, race conditions, metastability, and glitches being perhaps chief among them. There are advantages to asynchronous designs, usually lower power, faster, smaller gate count, and there are some problems for which a synchronous solution just isn't practical or even possible.Next dumb question on this . How are two individual signals put on the "clock" pin. They are separate signals that will never be there at the same time. One toggles 'Q' high and the next one will toggle 'Q' low. Do I put them both on separate edge detectors then into an 'or' gate? Or use separate edge detectors and diode 'or them?
"Clock" has subtly different meanings, depending on if you're referring to the "clock" input to your flip-flop or if you're referring to the synchronizing signal used in synchronous designs. For example, the processor in your computer has a "clock frequency" specification, which tells you the maximum frequency the logic can be "clocked" or synchronized. This is an example of a synchronous design. The clock pin on your flip-flop refers to an edge oriented control input, which "latches" the output of the flip-flop. In synchronous design, the synchronizing clock signal would be connected to the clock pin of the flip-flop. No other derived signal would be connected to this pin. All flip-flops clock pins would connect to he same synchronizing clock signal (assuming a single clock domain). Now sometimes, asynchronous derived signals are connected to the clock input of the flip-flop, though this is rare in contemporary design. In the asynchronous case, these signals aren't normally referred to "clocks", and they don't really have a formal name.You said, "That is not the correct definition of synchronous vs asynchronous. In both cases clocks are involved." But Brownout admonished me for using "clock" in describing my asynchronous type circuit. From every thing I've read lately when using the 'clock' pin you call it a clock. What is the correct term when using that pin?
Any small signal diode should do.Just a small signal Schottky diode, correct?
I have started a blog here:Give me some time. In awhile I will create a blog explaining the fundamentals of flip-flops.
I realize that I can use the S&R pins, and will use the R at power up to set the origin on the flip flop. But according to the "Cmos Cookbook" you run a bigger risk of a metastable state when using just S&R. And unless the input on S&R goes back to '0' after going to '1' to toggle your screwed. Since both inputs high are metastable. So I would still need the inverters (edge detector) just with a longer RC time to make sure the S&R return to '0'. The toogle signal is coming from a comparator so "could" both be active at same time.whoever said that set and reset signals on latches must persist to keep the latch outputs at their current state told you wrong. In your diagram, you can connect "on" to the set or preset pin (minding the activation level - high or low) and the "off" signal to the reset pin, if that's the functionality you need. This eliminates all those inverters, etc.
You're not screwed. It would only matter if you're connecting both Q and Q-bar to the same circuit, otherwise, the single output you're using doesn't change (using the 4013 as an example, check datasheet for a different device) If connecting both outputs, you can design for the condition. You have more ways of preventing metastability when using S/R inputs than using the clock.I realize that I can use the S&R pins, and will use the R at power up to set the origin on the flip flop. But according to the "Cmos Cookbook" you run a bigger risk of a metastable state when using just S&R. And unless the input on S&R goes back to '0' after going to '1' to toggle your screwed. Since both inputs high are metastable. So I would still need the inverters (edge detector) just with a longer RC time to make sure the S&R return to '0'. The toogle signal is coming from a comparator so "could" both be active at same time.