Clock pin on logic chip(another of my million dumb questions)

Alec_t

Joined Sep 17, 2013
14,280
Alec_T, it will just toggle from one state to the next.
In that case a CD4013 (or similar) D-flipflop should fit the bill. A fast-rising positive-going edge on the Clk input will change the state if the D input is connected to the not-Q output.
 

crutschow

Joined Mar 14, 2008
34,280
............ I'm using the word, "clock", in the only way I know how to phrase it. As each section of the circuit finishes it's job the next flip flop will start the following sequence. In this project that "clock" signal is from a comparator reaching a certain voltage. This is why it is what I understand to be an asynchronous system. What else would it be called?
.....
Synchronous and asynchronous refers to how the logic sequences.
An asynchronous system has no clocks so the logic outputs simply follows the signal inputs delayed only by any circuit propagation delays.
A synchronous signal performs the logic based upon the signals only when a clock occurs.
When the clock occurs has no bearing on whether the system is synchronous or asynchronous.
 

Thread Starter

shortbus

Joined Sep 30, 2009
10,045
Synchronous and asynchronous refers to how the logic sequences.
An asynchronous system has no clocks so the logic outputs simply follows the signal inputs delayed only by any circuit propagation delays.
A synchronous signal performs the logic based upon the signals only when a clock occurs.
When the clock occurs has no bearing on whether the system is synchronous or asynchronous.
"An asynchronous system has no clocks so the logic outputs simply follows the signal inputs delayed only by any circuit propagation delays."
Which is what I'm doing. Evidently I'm wrong in saying "clock" when using the 'clock' pin. What should I call it then? I can understand someone attacking on wrong syntax of words when two engineers are talking to each other. But this is an informal "teaching forum". This little rant is not meant toward you crutschow, just had to vent.
 

Thread Starter

shortbus

Joined Sep 30, 2009
10,045
Next dumb question on this . How are two individual signals put on the "clock" pin. They are separate signals that will never be there at the same time. One toggles 'Q' high and the next one will toggle 'Q' low. Do I put them both on separate edge detectors then into an 'or' gate? Or use separate edge detectors and diode 'or them?
 

MrChips

Joined Oct 2, 2009
30,706
That is not the correct definition of synchronous vs asynchronous. In both cases clocks are involved.

In a synchronous design, circuit elements (for example, flip-flops) are synchronized to the same timing signal, i.e. signals change simultaneously, taking propagation delay into consideration.

In an asynchronous design, there is no dependency for clocks to be synchronized to a common timing signal.

A ripple counter, for example, is an asynchronous design. Clocks are still present but one clock is derived from the output of the preceding stage. Subsequently, propagation delays will lead to "race problems" when attempting to encode/decode the outputs of an asynchronous counter resulting in "glitches" in the outputs of encoders/decoders.
 

MrChips

Joined Oct 2, 2009
30,706
Next dumb question on this . How are two individual signals put on the "clock" pin. They are separate signals that will never be there at the same time. One toggles 'Q' high and the next one will toggle 'Q' low. Do I put them both on separate edge detectors then into an 'or' gate? Or use separate edge detectors and diode 'or them?
It takes a bit of know-how and experience to be able to design with flip-flops comfortably.

Flip-flops are commonly used as "flags", i.e. a way of recording that an event has occurred.
There are two common types of flip-flops, D-type flip-flop, and J-K flip-flop. Either can be used as a flag. Which one to chose will depend on actual design requirements and other flip-flops needed in the circuit since they tend to come in pairs.

More importantly, flip-flop packages usually come with S-R functions, SET (or Preset), RESET (or Clear).

In order to design a flag function using a flip-flop, you can choose the S-R functions alone, or you can use the CLOCK along with the S-R functions.
For example, if you have two clock inputs, one to SET and the other to RESET, one solution is to use the first clock pulse to CLOCK the flip-flop Q to 1. Then use the second clock pulse to RESET the flip-flop.

Let me know if you need to see some example circuit diagrams of flip-flops.

Are you looking at using 7400 series TTL logic or 4000 series CMOS logic?
 

Thread Starter

shortbus

Joined Sep 30, 2009
10,045
MrChips any example will further my education.:) At the moment I'm limiting my self too the CD4xxxB series of logic. Just because they have a higher voltage level on the pins. And this is for my edm project that will have a lot of noise in it. When this one is successful I'll have a go with trying the lower voltage level logic. After all this time working toward this I want this circuit successful.

The flip flops are just to cycle mosfet drivers when certain parts of the circuit reach a set voltage level. If I knew more I'd try a micro, but I'm struggling to get this far.

You said, "That is not the correct definition of synchronous vs asynchronous. In both cases clocks are involved." But Brownout admonished me for using "clock" in describing my asynchronous type circuit. From every thing I've read lately when using the 'clock' pin you call it a clock. What is the correct term when using that pin?
 

Thread Starter

shortbus

Joined Sep 30, 2009
10,045
I'd diode-OR them right at the Clk pin. They both need to be fast-rising signals.
Thank you Alec, that was my first guess. But am wrong most of the time with electronics it seems.:) Just a small signal Schottky diode, correct?
 

WBahn

Joined Mar 31, 2012
29,976
Next dumb question on this . How are two individual signals put on the "clock" pin. They are separate signals that will never be there at the same time. One toggles 'Q' high and the next one will toggle 'Q' low. Do I put them both on separate edge detectors then into an 'or' gate? Or use separate edge detectors and diode 'or them?
What you are talking about is known as a "gated clock" which, in most instances, is a really bad thing. In general, asynchronous designs are much harder to do correctly because they are much more sensitive to several issues, race conditions, metastability, and glitches being perhaps chief among them. There are advantages to asynchronous designs, usually lower power, faster, smaller gate count, and there are some problems for which a synchronous solution just isn't practical or even possible.

To determine what you should do for this example, the details need to be laid out a bit more clearly. The two signals that you are talking about, where are they coming from and how clean are they? What do they look like? How long are they HI for when active? When you say that one toggles Q HI and the other toggles Q LO, this implies that Q is LO whenever the first signal is asserted and that Q is HI whenever the other signal is asserted. Is this guaranteed to be the case and, if so, how? It really doesn't make any sense to specify that a signal will cause another signal to toggle HI. Either it will cause the signal to toggle, or it will cause the signal to go HI. Which is it in this case?
 

Brownout

Joined Jan 10, 2012
2,390
You said, "That is not the correct definition of synchronous vs asynchronous. In both cases clocks are involved." But Brownout admonished me for using "clock" in describing my asynchronous type circuit. From every thing I've read lately when using the 'clock' pin you call it a clock. What is the correct term when using that pin?
"Clock" has subtly different meanings, depending on if you're referring to the "clock" input to your flip-flop or if you're referring to the synchronizing signal used in synchronous designs. For example, the processor in your computer has a "clock frequency" specification, which tells you the maximum frequency the logic can be "clocked" or synchronized. This is an example of a synchronous design. The clock pin on your flip-flop refers to an edge oriented control input, which "latches" the output of the flip-flop. In synchronous design, the synchronizing clock signal would be connected to the clock pin of the flip-flop. No other derived signal would be connected to this pin. All flip-flops clock pins would connect to he same synchronizing clock signal (assuming a single clock domain). Now sometimes, asynchronous derived signals are connected to the clock input of the flip-flop, though this is rare in contemporary design. In the asynchronous case, these signals aren't normally referred to "clocks", and they don't really have a formal name.

In terms of your design, without knowing more about what you're trying to accomplish, it would be difficult to give sound advice as to how to connect these pins, as others have already stated. In general, I would advise against connecting derived signals to the clock pin.
 
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Reloadron

Joined Jan 15, 2015
7,501
In an effort to simplify and hopefully convey where Shortbus is going with all of this I believe the attached image comes real close. Maybe not exactly but real close. :)

Stepper In Out.png
Here is basically what is going on as I see it. Starting with Vcap (lower left comparator circuit input). Vcap is a voltage sensed across an arc gap. The way that gap is maintained is monitoring the actual arc voltage. The actual size of the gap the greater the arc voltage and the smaller the gap the lower the arc voltage. VrefA R10 and VrefB R11set the comparator circuit limits (U6 A&B). The outputs of the comparator are fed to exactly as WBahn called it, a "gated clock" circuit and I am aware of his fondness of such circuits. :)

In this case the clock is a 555 astable multivibrator. U2 A&B form the gate which routes the clock pulses from the 555 to a 74193 4-Bit Up-Down counter. The routing simply determines if the counter counts Up or counts Down. The counter has a dual clock input, clock pulses into pin 4 while pin 5 is held low it counts Down, clock pulses into pin 5 while pin 4 is held low it counts up. Only output pins 3, 2 and 6 are used (A, B, and C). That data is passed along to a 74138 3 Line to 8 Line decoder where each 3 bit address drives one of 8 outputs Low. Those outputs drive a NAND gate (a continuation of the 7410 used to gate the clock). The rest is pretty evident driving a stepper motor. When the arc voltage is low the motor backs the torch head out and when the arc voltage is high the motor drives the torch head in. The EDM process short bus mentioned is slowly removing material (metal) from a work piece.

That my friends should be a good part of where Shortbus is trying to go with all of this. I think so anyway. :)

Ron
 

Brownout

Joined Jan 10, 2012
2,390
It's a gated clock, synchronous design. From a logical standpoint, the circuit is error-prone. From a functional standpoint, the errors are insignificant, and the circuit is self-correcting.
 

Thread Starter

shortbus

Joined Sep 30, 2009
10,045
Reloadron give sort of an idea of what I'm attempting, that was my inspiration for my journey. For what I'm doing the can be no 'system clock', the operations are too random. The next operation is dependent on the last one. I'm going to post a couple of files showing my thoughts on doing this. I don't show most of the normal needed things to make the circuit work though. No decoupling caps, no gate drivers and no values on the RC components. The comarators are only shown as a triangle with a letter in it to differentiate one from the others, and a "H' for high output and "L" for low output on one of them. The other two are used as a high output only.

I'll do the math for the other values if it seems workable. My circuit skills are only exceeded by my math skills(not so good). So look at my ideas at you own peril. I can build something from a schematic but making one is hard for a dummy like me.

edm 083.jpg edm 084.jpg
 

Brownout

Joined Jan 10, 2012
2,390
whoever said that set and reset signals on latches must persist to keep the latch outputs at their current state told you wrong. In your diagram, you can connect "on" to the set or preset pin (minding the activation level - high or low) and the "off" signal to the reset pin, if that's the functionality you need. This eliminates all those inverters, etc.
 

Thread Starter

shortbus

Joined Sep 30, 2009
10,045
whoever said that set and reset signals on latches must persist to keep the latch outputs at their current state told you wrong. In your diagram, you can connect "on" to the set or preset pin (minding the activation level - high or low) and the "off" signal to the reset pin, if that's the functionality you need. This eliminates all those inverters, etc.
I realize that I can use the S&R pins, and will use the R at power up to set the origin on the flip flop. But according to the "Cmos Cookbook" you run a bigger risk of a metastable state when using just S&R. And unless the input on S&R goes back to '0' after going to '1' to toggle your screwed. Since both inputs high are metastable. So I would still need the inverters (edge detector) just with a longer RC time to make sure the S&R return to '0'. The toogle signal is coming from a comparator so "could" both be active at same time.
 

Brownout

Joined Jan 10, 2012
2,390
I realize that I can use the S&R pins, and will use the R at power up to set the origin on the flip flop. But according to the "Cmos Cookbook" you run a bigger risk of a metastable state when using just S&R. And unless the input on S&R goes back to '0' after going to '1' to toggle your screwed. Since both inputs high are metastable. So I would still need the inverters (edge detector) just with a longer RC time to make sure the S&R return to '0'. The toogle signal is coming from a comparator so "could" both be active at same time.
You're not screwed. It would only matter if you're connecting both Q and Q-bar to the same circuit, otherwise, the single output you're using doesn't change (using the 4013 as an example, check datasheet for a different device) If connecting both outputs, you can design for the condition. You have more ways of preventing metastability when using S/R inputs than using the clock.
 
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