# Clock input for FPGA

Discussion in 'Embedded Systems and Microcontrollers' started by patheticz, Nov 4, 2009.

1. ### patheticz Thread Starter New Member

Nov 3, 2009
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is it possible to use clock generated from a DSP to provide clock signal for FPGA?

2. ### Papabravo Expert

Feb 24, 2006
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Of course! People do things like that all the time. You don't imagine that an FPGA cares where its external clock comes from -- do you?

3. ### patheticz Thread Starter New Member

Nov 3, 2009
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glad to hear that. =)
So if i am designing an embedded controller, which is inclusive of a FPGA chip and a DSP chip (which probably runs at 200 or 300MHz), the overall clock frequency of my controller can be generated from the DSP and not require any oscillator?

4. ### StayatHomeElectronics AAC Fanatic!

Sep 25, 2008
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Where is the DSP getting the 200 or 300 MHz?

5. ### patheticz Thread Starter New Member

Nov 3, 2009
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hmm...
so i guess i would need an oscillator nonetheless.
for some other forums i post reagrding clock frequency, i have been getting feedbacks that a crystal oscillator can generate a frequency thta is higher than its rated value?
is it true or have i misunderstood their term of dividing the frequency down?

6. ### StayatHomeElectronics AAC Fanatic!

Sep 25, 2008
1,020
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When I hear the phrase "dividing the frequency down" I think of starting out with, say, 200 MHz and dividing that frequency to get lower frequencies. 200 MHz -> 100 MHz -> 50 MHz -> 25 MHz -> ... The divide by 2 is very easy to get in digital logic.

I don't know anything about getting higher frequencies than rated on crystal oscillators ...

7. ### Papabravo Expert

Feb 24, 2006
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Yes it is true. The basic circuit is called a phase locked loop. It starts with a high frequency Voltage Controlled Oscillator. The output is divided down and compared with a lower frequency crystal controlled oscillator. The phase difference is used to adjust the VCO up or down until the phase coming out of the divider is equal to the phase of the reference oscillator.

Since crystal oscillators max out in the 60-80 MHz. region, it is the only way to get to higher frequencies.

8. ### patheticz Thread Starter New Member

Nov 3, 2009
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So if i am usign a Virtex 5 FPGA board, which has a on-board oscillator of 100MHz, but my design is able to run at 130MHz, my final controller will be able to perform at 130MHz?

And can you elaborate more on the Voltage Control Oscillator?
It is still a vague idea to me.
Thanks

9. ### Papabravo Expert

Feb 24, 2006
11,993
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A voltage controlled oscillator is also known as a voltage to frequency converter. You increase the control voltage and the frequency goes up. Conversely you decrease the voltage and the frequency goes down.
http://www.electronics-tutorials.com/oscillators/voltage-controlled-oscillators.htm
http://search.digikey.com/scripts/D...gle&cshift_ck=1544344610cs501690603&WT.srch=1

10. ### MaxSmoke Active Member

Oct 29, 2009
35
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While dividing down from a high frequency is one way, it does tend to limit your choice of frequencies. But, is a valid method. Using a PLL is very flexible and is another approach.

However, you can buy chips that will multiply up from a lower frequency to selectable multiples, or even a specific frequency from a given input clock (they have an in-built PLL). Here are just a few companies that specialise in programmable and selectable clock multipliers: Cypress Semiconductors IDT Silicon Labs

Designing your own PLL means you will need to consider the loop filter, to ensure loop stability over temperature, etc. Interesting subject in its own right, as there are all analogue PLLs, analogue & digital PLLs and all digital PLLs. The all digital PLLs use a digital loop filter.