Clock generation using VHDL

Thread Starter


Joined Oct 28, 2010
Is it possible generate a clock signal (let's say 100 kHz clock)just by using a VHDL code without taking any external inputs?

How can I write such a VHDL program?
I agree with Kubeek. Don't use this circuit for an FPGA especially. Routing differences alone will cause changes in frequencies.

Use an external oscillator.


Joined Mar 31, 2012
Technically you can use a ring oscillator circuit in VHDL. What is your application? Are you targeting an FPGA?
If it's targeting an FPGA, then you have to be really careful since FPGA logic is implemented in lookup tables, which are intrinsically glitchy.

Most FPGAs have an internal RC oscillator, used for loading the configuration data from a ROM of some flavor, but you may or may not be able to access it internally and you may or may not be able to keep it running once the configuration is complete. Even if you can, it is going to be a really poor reference, both in terms of accuracy and stability.

Use a decent crystal-based oscillator (or better, depending on your needs).