Clock Frequency limiter

Thread Starter


Joined Mar 15, 2006
I have attached a schematic which is part of a stepper motor control circuit (or hopefully soon will be). It was put together in B2Spice to help me work out this part of my control circuit.

Description of Schematic.
1. The attached schematic is meant to be part of the the current limiting mechanism for a unipolar stepper motor driver.

2. The function generator simulates the voltage from the motor current sensing mechanism (not shown on schematic), providing a sine wave of 2V peak to peak, fluctuating between 0v and 2v. to the inverting inputs of 2 comparators

3. The non-inverting inputs of those comparators have a simple voltage reference as the voltage against which the function generator's output is compared. In this example, they are set to 300mV and 1.6V respectively.

4. With this arrangement, the output of each comparator is Zero (0) when the sine wave voltage is ABOVE the voltage at the non-inverting inputs, and One (1) when it is below.

5. The outputs of the comparators are fed into a NEXOR (NOT XOR) gate. The output of which is HIGH when EITHER i) both of its inputs are high or ii) both of its inputs are LOW. Otherwise it's output is LOW. This output indicates when the sine wave voltage has either exceeded the upper comparators non inverting input voltage, or is below the lower comparators non inverting input voltage. In other words a transition from LOW to HIGH of this output occurs when either of the limits set by the comparators are "broken" by the sine wave. This provides the clock to a D Type Flip Flop.

6. The Output from the upper comparator is also fed to the DATA pin on the Flip Flop.

7. The Non Inverting output of the flip flop would be fed to a MOSFET Driver to control the gate on the power drive of the unipolar stepper driver.

So far so good. I have simulated it and it does what I expect.

However :

1. This circuit is a "bang bang" chopping type current regulator, in other words it switches the current on and off whenever the current sense voltage "bangs into" one of the set limits. The advantage of this is that you get a fixed current regulation.

2. A problem occurs however because the switching frequency depends on the motor supply voltage. The higher the supply voltage, the higher the switching frwquency (as the current through the motor winding will reach the upper limit quicker with a higher supply voltage).

3. Up to a point this is OK, but eventually the switching frequency becomes so high that the MOSFETs spend most of their time outside the full enhancement operating area and dissipate a lot of heat, due to the rise time of the MOSFET being a high proportion of the total on time.

4. I would therefore like to limit the maximum switching frequency by ensuring a minimum off time (in this particular case 10 micro-seconds).

In effect what I need is a circuit which :

When the current sense voltage exceeds the top limit, it switches off the MOSFET and starts a timer which inhibits the clock pulse which is generated when the current sensing voltage drops below the lower limit, if (and only if) that clock pulse arrives within 10 micro-seconds of the clock pulse which switched the MOSFET off. Once the 10 microseconds has passed, the clock pulse should be allowed through to the flip flop.

If anyone could help with such a circuit I would be most grateful. I know I need some kind of non-retriggerable one shot and probably some "AND" gates to do this, but so far I could not get anything to work.

I have also attached a trace from the simulator showing how the logic currently works. The key to the graph is :

1. Lower thick black trace is the output from the Flip-Flop (marked "Gate")
2. Lower red line (marked "Data") is the output from the upper comparator as fed into the Flip-Flop data input.
3. Lower blue trace (marked "Clock") is the output from the NEXOR Gate and is the clock into the Flip Flop
4. Pink Horizontal line at 300mV is the voltage on the lower comparator non-inverting input
5. Blue horizontal line at 1.6V is the voltage on the upper comparator non-inverting input
6. Sine wave is used to represent the motor winding cirrent sensing voltage
7. The square waves going between 0V and 5V are the ouputs from the comparators and is included for completeness to show the outputs swhitching when the sine wave passes through the "limits".

Many thanks


Joined Jan 28, 2005
I would like to compliment you on such a well organized posting. It ranks among the best I have seen on this website to date.


Thread Starter


Joined Mar 15, 2006
Originally posted by hgmjr@Apr 1 2006, 05:18 PM
I would like to compliment you on such a well organized posting.  It ranks among the best I have seen on this website to date.

[post=15696]Quoted post[/post]​
Well thank you for the compliment, it is much appreciated. I think it only polite when asking people to give their valuable time and knowledge to assist me that I try to explain what I am asking for help with as clearly as possible (at least to the best of my limited electronics knowledge).


windoze killa

Joined Feb 23, 2006
Originally posted by bigbigblue@Apr 6 2006, 10:03 AM
Can anyone offer any help with this?

[post=15871]Quoted post[/post]​
The simple answer I can see would rely on limiting the I/P voltage as this controls the frequency. If you know what freq you want to stop at and hence what voltage then you could use a zener diode to stop the voltage going higher. As I said this is the simple method but I am sure you could also use a more complex regulator circuit to do similar.


Joined Oct 14, 2005
You are right, a non-retriggerable monostable and an AND gate would work. Use the output from the flip-flop (MOSFET off signal) to trigger the monostable, and AND the active low output of the monostable with the output from the lower limit comparator. This would enforce a minimum off time.

Use 74221 dual non-retriggerable monostable (simpler solution) or built one from 555 (need inhibit circuit to prevent retriggering).