Hi,
I am extremely new to circuits and stuff (this is my first semester) and my teacher wants us to make a clock divider with d-flip-flops and 4:1 mux. I honestly have now idea what a clock divider is. I understand DFFs a little and i know how to write a 4:1 mux in vhdl, i just don't know how to implement them to make a clock divider. Here are the instructions:

"Construct a Selectabel Clock Divider with possible divide choices of 2, 4, 8 and 16. This should take 4 D-Flip-Flops with each Q output going into a 4:1 Mux. Create A VHDL model for the clock divider. Within this file, you will use structural VHDL to instantiate the four DFFs and wire them up in a clock divider configuration. Within this file also create the 4 to 1 mux using behavioral VHDL."

Like I said i really have no clue where to start. Our book doesn't have much on clock dividers and we haven't been over them in class. Any help, VHDL code or anything else would be great.

Thanks!

 

I can't help you with the VHDL part, but I can tell you what circuit you are looking for.

First of all, do you have access to the textbook "Digital Desing", by M. Mano? It has a very good picture of a DFF counter.
In short, what you do to build it is the following:
For each of the 4 DFFs of the counter

• Connect its Q' output to its D input.
• Connect its clock input to the previous DFF Q output. For the first DFF connect its clock input to the system clock.
• Take the count output from the Q output of each tier.

In that way, you will have 4 Q outputs. They will make a full period every 2-4-8-16 cycles of the original clock. Thus you have successfully designed a clock divider.

All you have to do now is take those outputs and connect them to a 4-to-1 MUX. That way you can select one of them each time.

 

Hi,
I am extremely new to circuits and stuff (this is my first semester) and my teacher wants us to make a clock divider with d-flip-flops and 4:1 mux. I honestly have now idea what a clock divider is. I understand DFFs a little and i know how to write a 4:1 mux in vhdl, i just don't know how to implement them to make a clock divider. Here are the instructions:

"Construct a Selectabel Clock Divider with possible divide choices of 2, 4, 8 and 16. This should take 4 D-Flip-Flops with each Q output going into a 4:1 Mux. Create A VHDL model for the clock divider. Within this file, you will use structural VHDL to instantiate the four DFFs and wire them up in a clock divider configuration. Within this file also create the 4 to 1 mux using behavioral VHDL."

Like I said i really have no clue where to start. Our book doesn't have much on clock dividers and we haven't been over them in class. Any help, VHDL code or anything else would be great.
Thanks!

Brush up your Google-fu. And you will easily find answer to these questions. A mux is something that most books in VHDL have example of. But I can give you a clue

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