Heya,

I'm following http://www.irf.com/product-info/audio/classdtutorial.pdf as a guide to design my own Class D audio amplifier for at home fabrication.

Can anyone explain exactly what modulation factor represents in PWM modulation. I just assumed it defined the percent of intended signal you can actually produce in the given modulation scheme. That being said, I can't figure out exactly why it impacts the breakdown voltage for the MOSFET bridge so much?

Any ideas or references would be groovy, I'm new to Audio.

Cheerio,

James

 

I think the modulation factor is the ration of the peak voltage of the audio signal to the peak of the triangular signal. Both signals referred to the input of the comparator.

 

The concern may be to insure that the amp doesn't end up applying DC to the speakers (100% duty cycle).

 

hmmmm. Both good answers.

If it were to restrict 100% duty cycle, than it would imply my design must limit this, which won't be the case nor is this mentioned in the application note from IR.

If it were a percentage of peak output defined by saw tooth limitations, than shouldn't that also be a design contraint built into the design? Otherwise, I should theoretically easily be able to just provide a reference voltage above the sawtooth maximum and hold my comparator output high and saturate the outputs, thus in effect achieving nearly 100%.

I spoke with a Control System Doctor (Ph.D) at work and he said it is inherent in PWM to only be able to achieve 85% (recently 90% has been possible) at best of what you desire. His only explanation was that it was so through simulations, which I assume he has performed on instance as we are involved in the BLDC servo drive business, which is in effect the same technology.

I feel his comments are related to attempting to provide an ideal sine wave, whereas other waveforms may actually have differeing modulation factors.

I'm still a bit fuzzy but perhaps it will just be one of those things I know but never truly understand

 

Have a look at the link, it may be helpful:

http://www.nxp.com/acrobat_download/applicationnotes/AN10436_1.pdf

I am not sure what is the maximum efficiency you can achieve but don't always believe doctors, they don't know everything

 

O I assure you I know, after all I have a Masters' and feel none the wiser

Not much at that link. Seems odd it is such an important factor in selecting appropriate FETs/IGBTs and I can't pull up an exact enough definition.

The closest I come is with AM radio where they define it as the percent of transmission. Ideally it is nearly 100% but if your carrier amplitude is too small for the signal amplitude, you clip some of your signal out of the modulated signal, and thus your modulation factor seems to start to decrease. I can't seem to attach this same idea to PWM audio modulation in my head, maybe a mental block?

If no more fresh ideas, I'll just bury the hatchet and use 1/0.85 additional safety factor on the breakdown voltage of any switched FETs I ever use.

O woe is me

 

Hello,

Here is a link about "Understanding Class-D amplifier power supply requirements".
http://www.audiodesignline.com/howto/208700453

Greetings,
Bertus

 

Maybe you have a master but you don't know how to select a MOS or IGBT for your application and you are stacked on an equation. It is not necessary to know this equation to choose the transistors. This is just a way to do it but if you know what are you doing you don't need this equation. You are designing the circuit, you know the maximum voltages and currents, switching times etc, just sum all these and choose the appropriate transistor.

 

Thanks for link Bertus, I'll have a gander. Mike, the tricky thing with switching applications are all of the transient surges. Many of them are hard to predict as layout has much to do with this, and although I do use the standard 1.5x safety factors, which should be more than enough for any surges, such a factor as 1/0.85 from modulation factor would seriously cramp into my overall safety factor if unaccounted for.

 

I am also looking at that App note AN-1070. I believe the modulation index (M), or output duty cycle, is in the equation only to put the MOSFET voltage in certain terms (mainly output power) to be seen early on in the design. I get the same equations for the full and half bridge, if I assume no loss in the output LPF. So here, I think M is the duty cycle in terms of the desired full output power.

M is ideally 100% at full power right? Since it would be pushing the load to each rail, the duty cycle would need to vary between 0% all the way to 100% (maximum modulation around the carrier). 0% duty cycle corresponds to DC from one rail, and 100% is DC in the opposite direction and 50% is 0. It's easier to think of max output power with a single mode sine wave.

Assume ideal switches, then Vcc = Vds. For the full bridge, the average power supplied is D*(Vds^2)/Rload integrated from 0 to M with respect to D. If that's the output power with a lossless output LPF, then I solved for Vds to get it in terms of output power (and M). With a half bridge, it's easy to see that the Vds will be double.

 

I am also looking at that App note AN-1070. I believe the modulation index (M), or output duty cycle, is in the equation only to put the MOSFET voltage in certain terms (mainly output power) to be seen early on in the design. I get the same equations for the full and half bridge, if I assume no loss in the output LPF. So here, I think M is the duty cycle in terms of the desired full output power.

M is ideally 100% at full power right? Since it would be pushing the load to each rail, the duty cycle would need to vary between 0% all the way to 100% (maximum modulation around the carrier). 0% duty cycle corresponds to DC from one rail, and 100% is DC in the opposite direction and 50% is 0. It's easier to think of max output power with a single mode sine wave.

Assume ideal switches, then Vcc = Vds. For the full bridge, the average power supplied is D*(Vds^2)/Rload integrated from 0 to M with respect to D. If that's the output power with a lossless output LPF, then I solved for Vds to get it in terms of output power (and M). With a half bridge, it's easy to see that the Vds will be double.

First of all, I am excited that you are challenging this division by M in the app note as well to gain a deeper understanding. I have bounced this one off lots of people and nobody really had much to say about it.

Let me first cover the grounds of my understanding before delving into the mathematics with you.

1. In a half bridge configuration, the lower FET will see at worst Vcc*2 (i.e. its source sits at -35V for example and when the upper one switches on it will be a Vds on the lower of 70V). That is clear and ignores transients.

2. With that in mind, ignoring transients again, I cannot see how with 50% or 100% duty cycle this could be any 'higher' than Vcc*2. Sure with duty cycle the output side of the inductor in the LPF is obviously seeing differently, but the switches themselves, I do not see it.

So how then does duty cycle become a factor in selecting what Vds your mosfet need cope with? Personally I would just do 2x the rated voltage to allow for transients and ignore duty cycle all together. The switching speed and parasitic inductances along with bus pumping would be the only real sources of concern above and beyond this in my opinion.

In the app note, they use a modulation factor of 85%. This doesn't make much sense to me. Surely as you say there are going to be times when the duty cycles peaks out at 100% as it drives to catch up.

 

O and by the way, I have my design up and running if you are curious of anything I experienced along the way. Boy can it ever sound great, at least for a low cost passive crossover floor standing configuration. Got two 350W 36V power supplies driving the +- and whammo can it ever go loud at 2x120W with these great speakers I found on ebay with 10 inch drivers for bass.

 

Apologies, I was not real clear in my previous post about this. It is my understanding that the modulation index (M) is not the same as duty cycle (D). If we PWM around the carrier, the duty cycle changes -> Extremes: If D changes as much as to go down to 0% and up to 100%, then the modulation index would be equal to 1. If D stays at 50%, then M=0. That is why I integrated the output power from D=0 to D=M.

 

So I agree with your statement that in half bridge it is easy to see that Vds will be double.

What is still unclear is why IR divide by M and have it set to 0.85 in their calculation. If M < 1, we know it is not full power, yet it is 'less' than full power but the division by 0.85 demands a higher rating of the reverse breakdown voltage of the mosfet. Other than transients, I do not see how > 2xVds can be achieved in a half bridge. Maybe they assume a relationship between power and bus pumping and use M as a representative variable of power? Regardless, I would imagine bus pumping to be at its worst in and around 95% duty cycle, as the bus can pump up quick enough, irregardless of duty cycle (assuming < 100%).

I cannot understand how less than full power makes me rate my mosfet to more than 2xVds based off duty cycle.

Regards,

James

 

I don't think it is bus pumping because that does not occur in a full bridge topology and the modulation index is in the denominator for both half and full bridge equations. I agree, it's clear that BVdss can't be more than Vcc or 2*Vcc for full and half respectively (aside from pumping and circuit related issues). Thinking of it that way, it's not making intuitive sense to me either.

So, I'm thinking of it this way: Assuming that we understand that BVdss and Vcc are nearly the same worst case, we need to choose Vcc (thus BVdss) to obtain the output power we want. Since it is unrealistic to modulate 100%, we need to increase the voltage Vcc (thus BVdss) in order to achieve the desired output power. So; M is de-rating the output power, or buffering the voltage we need.