Class C amplifier design

Discussion in 'Homework Help' started by ransidesilva, Dec 15, 2013.

  1. ransidesilva

    Thread Starter New Member

    Sep 1, 2009
    Hi All,
    I am new at RF circuit Design and as part of my coursework I have been given the task of designing Class-C power amplifier.
    Design spec
    1. 50ohm source and load impedance
    2. 21dBm output power with a gain of 10dB
    3. Transistor to use 2N3866
    4. DC supply voltage 12V
    5. Operating frequency 433MHz
    6. Use L networks for matching
    7. User ADS ( but I use LTSpice for the spice simulation stuff )
    Methodology that I followed,
    1. Find the impedance transformation networks using the transistor large signal model for input and output.
    2. Plug in the transistor model, impedance transformation networks ( L networks ) , in the Class C topology and see if we get the required output and input voltages ( Voltage gain ) transient Analysis
    3. * for point 3 Actually I am not sure what we can simulate , cant we simulate to a reasonable extent the output power and gain ( ignoring board layout considerations ??) , I found the following material on the subject so far with regards to simulation :

    As I was unable to get the required (voltage gain) I was given a working circuit. The simulation does not give the required gain of 10dB but the constructed project does. Of course the board has been tuned a bit but as a starting point the following circuit has been used as the output of the Simulation stage.

    The Questions I have
    1. What is the purpose of L5 inductor, i don’t understand it. If the supply voltage falls below 0.7 the transistor should not conduct, what is the point of shorting the base current to ground ?
    2. The L2 value is obtained by combining the RF choke and the high pass L network shunt L. ( that I understood )
    3. Why is the Vout negative going pulse not clipped? as the transistor should be turned off during this period.
    4. What is the correct way to calculate the input power Vs output graph ( which to me seems meaningful and feasible

  2. bertus


    Apr 5, 2008
  3. ransidesilva

    Thread Starter New Member

    Sep 1, 2009
    Hello Bertus,

    sorry mate !!!!
  4. t_n_k

    AAC Fanatic!

    Mar 6, 2009
    I would be wary of Spice simulations of Class C RF power amplifier design notwithstanding the claims of the validity of that approach. Motorola pioneered credible RF transistor amplifier design methods and provided information in that context - such as one finds in their application notes AN282A & AN1526. The attached pdf has relevant data for the 2n3866 in that design context. This might provide you with a comparable method against which you can benchmark / verify your already working amplifier.
    Last edited: Dec 15, 2013
  5. t_n_k

    AAC Fanatic!

    Mar 6, 2009
    Presumably you know Class C is biased beyond cut-off. Hence the DC conditions for base & emitter are tied to 0V - the base via L5 and the emitter directly. L5 provides a high impedance to the input RF signal - preventing RF shunting to ground whilst permitting the correct DC bias condition at the base.

    The collector load would be resonant at the input RF frequency. Whilst the collector drives "distorted" current pulses [a switch like behaviour] to the collector load, the resonant load condition ensures the collector voltage usually resembles a reasonable sinusoidal form. Excessive overdrive might degrade the output purity. In any event, one usually finds additional matching circuitry on the output side which assists also in the cleaning up of the "amplified" RF signal.
  6. tbinder3


    Jun 30, 2013
    I believe they wanted a higher order filter is all. I took like 15 second look and was a super small picture, but believe so.

    In an ideal BJT you assume iB≈0 and that iC≈iE, doing so you can calculate the base potential, and then the emitter potential for NPN: Ve=Vb - 0.65v and PNP: Ve=Vb + 0.65v, then start solving for current.

    However, keep these notes in mind:

    For an NPN transistor, active mode requires Vc − Ve > 0.2 V. For a PNP transistor, active mode requires Ve − Vc > 0.2 V. If this condition is violated, the transistor is saturated, and the analysis cannot continue using these simple rules.
  7. t_n_k

    AAC Fanatic!

    Mar 6, 2009
    This is most likely not the case. Inductor L5's reactance is sufficiently high at 433MHz that it will have little influence on the behavior of the input impedance matching components C5 & L1 - that being the primary purpose of the latter two elements. As I indicated in an earlier post the purpose of L5 is to provide a high RF signal shunt impedance to ground at the base, but (concurrently) a low DC resistance path to set the base (quiescent) bias to ground potential - the same potential as that of the grounded emitter.
    Last edited: Dec 17, 2013
    tbinder3 likes this.