In a forward clamping circuit, during the negative cycle, the diode conducts and capacitor is charged to the peak value of 5 volts(assuming a 10V p-p source).

The diode drops 0.7V, so 4.3 V across the capacitor is stored.

My question is, the source is at it's peak value only for an instant. So for that instant in time, the KVL across the loop is satisfied. During all other time instants of the negative cycle the KVL is not satisfied since the voltage across the capacitor and diode together is 5V throughout the negative cycle( neglecting the short time it takes for the capacitor to regain it's lost charge). What am I missing?

Also, sources are generally considered to be the rms value. Or in this case 5/1.414 V . So shouldn't the capacitor charge only to this value?

 

KVL is always satisfied. post your circuit...

 

The diode voltage drop must always be equivalent to the algebraic difference between the instantaneous source voltage and the capacitor voltage. KVL will always apply.

 

Panic Mode,

Check here .....
http://www.allaboutcircuits.com/vol_3/chpt_3/7.html

 

The diode dropping the appropriate voltage to satisfy KVL is confusing me.

If the diode conducts, it will drop 0.7V. Isn't this the condition for the junction gap to be overcome to allow for a conducive device?

It cannot drop lower than 0.7 V and conduct at the same time?

Secondly even if we were to to assume that diode drops the appropriate voltage differential between source and capacitor voltage, say at time instant when voltage source is 1V, the diode will have to drop 3.3V in the reverse polarity!? Doesn't that seem illogical?

 

Post your circuit, and remember, electrons are never wrong. They are not capable of disobeying the laws of physics. Any circuit that doesn't work the way it should is your fault.

 

The circuit is in the attachment. The forward clamping circuit in fig.a

 

When the output of the generator is positive, it will be +5 volts peak, as per the label. This voltage will suck electrons through the diode so that they lodge on the right plate of the capacitor. After that moment, the diode will be reverse biased for all remaining voltages that this generator can provide.

With any load at all, the output will be pretty much a sine wave of 9.3 volts peak to peak with its most positive excursion being 0 volts and it most negative excursion being -9.3 volts. The diode will only conduct in that tiny piece of time when the generator recharges the capacitor to the peak voltage minus .7 volts. At all other times, the diode is reverse biased and stops all current.

Does that tell you what you need?

 

The diode dropping the appropriate voltage to satisfy KVL is confusing me.

If the diode conducts, it will drop 0.7V. Isn't this the condition for the junction gap to be overcome to allow for a conducive device?

It cannot drop lower than 0.7 V and conduct at the same time?

Secondly even if we were to to assume that diode drops the appropriate voltage differential between source and capacitor voltage, say at time instant when voltage source is 1V, the diode will have to drop 3.3V in the reverse polarity!? Doesn't that seem illogical?

Not illogical at all. A diode can withstand any voltage drop less than the forward conduction voltage of about 0.7V without conducting at all up until the reverse breakdown voltage is reached (which we are assuming does not happen here). So if you reverse bias the diode by 10V, it will sit there looking stupid with -10V across it and no current flowing.

Also, circuits don't know anything about RMS -- they respond to the voltages and the currents they see right now, at this instant. Hence they respond to the instantaneous signals. RMS is merely a convenient way for humans to describe certain average traits of a voltage or current waveform over an extended period of time.

 

Things seem a lot more clear now. Let me lay down my understanding of this concept.....

In the very first negative cycle, the diode begins to conduct once the source voltage(Vs) exceeds -0.7V. Current flows across the diode, charging the capacitor till Vs=-5V peak leaving capacitor voltage(Vc) at 4.3V.

Now this is crucial, when the sine wave amplitude falls down from -5V to -4.9V, the diode is reverse biased and doesn't draw current. This continues till the next negative cycle.

Let's assume during the +ve half cycle, Vc discharges through the load leaving it at 4V.

Now during the 2nd negative half cycle, the diode remains reverse biased until Vs exceeds -4.7V(Vc + diode voltage drop) where it begins to conduct, recharging the capacitor to 4.3V again. This process repeats, as the diode drops the appropriate reverse voltage across it's technically open circuit leads as mentioned by WBahn.

Am I right in my analysis?

 

You have the diode backwards in your mind, making the polarities backwards through your entire explanation. Otherwise, you are correct. Backward polarities are the lesser part of understanding this circuit.

 

Thanks a lot for the help guys. It helped me understand an important concept that I hadn't seen earlier. Cheers