Hello everyone,

I need help in revising my attached design of a combinational digital circuit that will drive the F segment a seven segment display to use 2 input NAND gates please.

Thanks very much.
I appreciate your help.
Thanks

 

Can you convert the basic 1 and 2 input gates (INV, AND, OR) into equivalent circuits that only use 2-input NAND gates?

Can you convert a 4-input AND gate into an equivalent circuit that only uses the basic gates (INV, AND, OR) listed above?

 

I'm in a daze right now about your reply. I think iv been thought about it. i'll go look @ my notes.
Appreciate your reply

thanks a lot.

 

Yes i know the nand gate which is the AND with the zero @ the output and also having 1 input AND ( which is the 2 inputs joined together).
Yeah I know those..

 

Yes i know the nand gate which is the AND with the zero @ the output and also having 1 input AND ( which is the 2 inputs joined together).
Yeah I know those..

This wasn't what I asked. A "zero @ the output" is more properly called an "inversion bubble". The phrase "zero at the output" is too easily misinterpreted as meaning the logic value at the output is zero (a logic False).

What circuit do you think is created by joining the two inputs of an AND gate together?

Here are the questions I asked phrased a bit more explicitly:

If I give you a box of 2-input NAND gates, do you know how to take some of them (how ever many you need) and construct a circuit that has the same input/output relationships as an inverter? As a 2-input AND gate? As a 2-input OR gate?

Then, if I give you a box with nothing but 2-input AND gates, could you construct a circuit, using as many of those as needed, that has the same input/output relationship as a 4-input AND gate?

 

hahaa......
you've knocked me into coma now. im new to electronics, please go easy on me. Im only just getting used to logic gates. i dont know what to say. i have to go read my notes and get back to you on that one.

I appreciate your replies.

 

Here's a bit more of a hint.

Take a 2-input NAND gate and tie the inputs together (which makes it a 1-input gate). What logic function do you get as a result?

Now take a 2-input NAND gate and follow it with a 2-input NAND gate configured as described above. What logic function do you get?

 

the answer to the first question is a NOT gate.
and the second answer is a double inversion at the output of the second one (or A into the first then A' at it's output then A' into the second and A at the second's output.

Hope ive got them right.
I like the way you challenge me. Its good to learn this way.

 

the answer to the first question is a NOT gate.

Correct.

and the second answer is a double inversion at the output of the second one (or A into the first then A' at it's output then A' into the second and A at the second's output.

Remember, the first NAND gate does NOT have it's inputs tied together. It has two inputs, A and B. The output, call it C, of this gate then goes to both of the inputs of the second gate. The output of the second gate, call it Y, is the output of the overall circuit.

So draw a truth table for the inputs A and B and the output Y for this circuit.

Hope ive got them right.

You're on the right track, anyway.

I like the way you challenge me. Its good to learn this way.

Good, because that's the way I generally operate.

 

thanks very much. I 'll do that and let you know.
Very nice to know there are people out here to helping
novices like me.
I'm off to work and you may not hear from me for a while
as my shift can run for over 12hrs.

I appreciate your help.
Thanks very much again.

 

Helloo everyone,

Ive been asked to revise my design to use 2 input NAND and i wondered if i was doing the right thing.

I did the truth table and i have attached for anyone to view to see if im doing the right thing.

 

Helloo
I did the truth table and i have attached that to my new thread as i cant find the attach button to put it on here.

Thanks

 

Please don't start a new thread. To post the attachment, use the Go Advanced button at the bottom of the Quick Reply dialog box. Then use the Manage Attachments option.

 

I looked at your table. Go back and check on what the truth table is for a NAND gate.

 

Hello,

I have merged the two threads on the same subject.
The posts will show in the timeline order.

Bertus

 

Thanks very much for merging the thread. I appreciate it

 

Sorry I have been away working and im currently using my phone which cant do as much as a computer. Ill hav a look at the nand truth table again. Thanks a lot.

 

Thanks very much for merging the thread. I appreciate it

 

Yes I made mistakes on the output c which should have been just the INV of the output of an AND gate . So state c output should be 1110 then output Y should be the INV of state C. So that should be 0001

 

Yes I made mistakes on the output c which should have been just the INV of the output of an AND gate . So state c output should be 1110 then output Y should be the INV of state C. So that should be 0001

And which logic function does that describe?

In other words, a NAND gate with the two inputs tied together implements an INV gate. What gate does a NAND followed by an INV gate (constructed with another NAND gate) implement?