# Capacitance Multiplier

Discussion in 'General Electronics Chat' started by KCHARROIS, Mar 17, 2013.

1. ### KCHARROIS Thread Starter Active Member

Jun 29, 2012
302
8
Hello Everyone,

I'm looking into building a capacitance multiplier so I looked up a few circuits but I can't seem to grasp on how they work.

In the first picture I see that theres positive and negative feedback. R1 and C1 form an RC circuit but thats all can see...

In the second one, I see two current mirror circuits and thats as far as I can get to be quite honest.

An explanation or some insight on what I'm not seeing would be great.

Thanks

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2. ### t_n_k AAC Fanatic!

Mar 6, 2009
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The first circuit isn't an ideal capacitance multiplier. It turns out to equate to a multiplied capacitance Cx plus an equivalent series resistance Rs.

Cx=C1*(R1+R3)/R3 - rather than the approximate value C1*R1/R3

Rs=R1||R3

The approximations work with the high R1 value [10 MΩ] and relatively much smaller value of R3 [1kΩ]

The presence of Rs means this multiplier is not suitable for high Q applications.

As for the second circuit one would probably have to read the associated patent to gain a clear understanding of the operation.

3. ### KCHARROIS Thread Starter Active Member

Jun 29, 2012
302
8
Ok let me bring the circuit down to a finer level... 2 transistors and 1 capacitor. I'm assuming the circuit is going to be pulsed because the capacitor will block DC. Its a current mirror circuit but how does this prove capacitance multiplication.

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4. ### t_n_k AAC Fanatic!

Mar 6, 2009
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Assuming [for the moment] that the transistors form an ideal current mirror then whatever current flows into the capacitor [& Q1] is mirrored in the parallel path [Q2]. So the overall result is that the total current flow into the circuit [node 18] responds to any source input stimulus as if there was a capacitor of twice the value of C1 connected from node 18 to ground.

In a real situation this is somewhat modified by the non-ideal Vbe drop in the transistors.

5. ### KCHARROIS Thread Starter Active Member

Jun 29, 2012
302
8
Referring to Fig.1, show is a schematic diagram of a conventional capacitance multiplier circuit. The circuit includes a fist npn transistor Q1 and a second npn transistor Q2 coupled in a configuration that forms a current mirror.Alternatively, the current mirror can be formed by a single, multiple collector device rather than the separate, matched devices Q1 and Q2 shown. The transistor Q2 is scaled in area to be K times the are of transistor Q1. A capacitor C1 is coupled to the transistors Q1 and Q2 as shown. The current through capacitor C1, IC1, also flows through the first transistor Q1. Thus, the current through the second transistor Q2, IC2, a is approximatly K x Ic1. The impedance at a node 18 is primarily capacitive and has an effective capacitance of approximatly C1 X (1 + K). It should be noted that the circuit does not show a bias network for the transistor Q1 and Q2. The bias network supplies a current to transistors Q1 and Q2 such that the net current into the circuit at node 18 is close to zero.

This is the info that came with the schematic from my previous post I see what your trying to say but was is K exactly?

Thanks

6. ### t_n_k AAC Fanatic!

Mar 6, 2009
5,448
790
If Q1 & Q2 are identical [matched - in my interpretation of that term] then the current in Q2 exactly mirrors the current in Q1. In that case the factor K would be unity (=1). Curiously the explanation says the transistors are "matched" but suggests they are scaled in die area to give an effective gain K in the current mirror behaviour. So by scaling the transistor areas one achieves a higher than unity ratio K for the current mirrored from the C1 path to shunt to ground - from node 18. This shunt current mimics the capacitor current and thereby appears as an equivalent parallel capacitance of K*C1.
The total effective capacitance is then the parallel combination of C1 & K*C1 or (1+K)*C1.

Last edited: Mar 17, 2013
7. ### t_n_k AAC Fanatic!

Mar 6, 2009
5,448
790
It may now occur to us that the original schematic for the patented circuit is designed to offset any anomaly due to the transistor Vbe issue mentioned earlier. The inclusion of the op-amp ensures the low side of the capacitor sees a virtual ground potential. So the input sees only an effective capacitance to ground.