# Cant Figure out transient.

#### saint_jay77

Joined Oct 19, 2006
26
Hi,
THE FACTS
I have a circuit here in PDF and am trying to figure out why i have a transient at the gate of the second FET(point A on the schematic). The schematic shows the 2 x 10K resistors forming a voltage divider and the signal seen (sawtooth wave) was the outcome. This was not what i was looking for!!!!!!

WHAT I TRIED; EXPERIMENTAION
It was found that when i took off the connection of the 10K from the gate of FET IRFB23N15D to the ground and replaced the other 10K with a 0 ohms resistor there was a presence of trasient underdamped response waveform.
The BMP files attached shows the waveforms.

I know this is characterised my the second order diffential equation in which ther are 2 energy storing elements. I would like to know how i can get a square wave (nice square edges) at the gate of the FET IRFB23N15D at point A on the schematic.

Thanks to anyone who can explain what is goung on. I am speculating that the gate source capacitance and the drain source capacitance is the culprit for the high rise time and the transient.

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#### John Luciani

Joined Apr 3, 2007
475
You are limiting the gate drive current with a high series resistance.

In your first picture you have removed the 10K divider and the IRFR3412 (Q1)
is able to discharge the Cgs of the IRFB23N15 (Q2) with a low impedance (Rds(on)). This
is why the fall time is quick. When Q1 opens you are charging the Cgs of
Q2 through the LED and 10K resistor. The 10K resistor limits the amount
of current to charge the Cgs of Q2.

You need to charge and discharge the Cgs of Q2 with a low impedance.
Take a look at FET driver ICs and circuits. These circuits use two FETs in
a complementary manner.

(* jcl *)

---
www.luciani.org

#### nomurphy

Joined Aug 8, 2005
567
The second FET at point A is not doing much, changing it to a smaller lower capacitance device such as an MMBF0201 or 2N7002K should resolve your problem.

Also, regarding the two 10K resistor gate divider, you don't need that much voltage on the gate -- make the top resistor ~20K and the lower resistor ~5K (which will compound your problem if you don't change the FET type as suggested).

And, change the drain resistor from 100K to ~20K.