What if instead of tracks I used copper fill zones? Is it better ?Some thoughts on layout.
0.8/1mm tracks are fine but ideally need 2oz copper to cope with peak currents, you'd be OK with 2mm tracks on 1oz - and before anyone says they can be smaller, yes they can, but switching regulators, in my experience, are fickle beasts and a little stray inductance can cause all sorts of side effects. I prefer to size for the peaks rather than the low averages.
Tracks carrying peaky currents and switching transients must be as short as possible - that especially applies to the switch-diode-coil connection and to a lesser extent the input capacitor/switch connection. The coil/output capacitor connection is less critical. The reverse is a complete ground plane. Nevertheless, cosider how currents circulate within the ground plane. On the conduction cycle current flows from C1/C2 through U1, L1 and C3/C4 then via the ground plane back to the ground side of the input. Therefore keeping the length between C1/C2 ground and C3/C4 ground short is beneficial (not least for EMC). Similarly on the discharge phase the current is L1, C3/C4, D1 and back to L1 via the ground plane.
Here's my take on the layout - only one regulator shown with reverse protection MOSFET... many other layouts are possible...
View attachment 249103
Yes, a P-Channel, but wired 'backwards'. Pin 2, the tab, is the drain. Normally the drain on a p-channel would be -ve wrt the source, but here its more +ve. Simplistically, unlike a bjt where the charge carriers create depletion zones and therefore polarity is important, in an enhancement MOSFET the gate charge 'opens' the width of the free charge carrying zone between drain and source, reducing its resistance, but there's no 'junction' as such so the channel works pretty much the same in either direction. Current initially flows through the drain-source diode, now forward-biassed, which raises the source potential more +ve wrt the gate (tied to ground, so now more -ve wrt source), turning the P-MOSFET on and reducing the voltage drop to a few mV.And are you using a p channel MOSFET here ? Pin2 of the MOSFET is source or drain?
The main issue is to minimise track lengths between chip, coil and diode and, less critically, coil and output capacitor, as this is where the main current flows are and we want to minimise the parasitic inductances. Track width is less of an issue, but thermal reliefs break the flow and actually increase the effective length. Plus large zones above the ground plane create parasitic capacitances which resonate with these parasitic inductances and, driven by the fast switchng transients, can create opportunities for high-frequency parasitic oscillations causing various overheating, and other component-stressing, issues. Therefore we want to minimise the area of copper in those tracks without reducing the current carrying capacity or increasing track heating. While less critical at these sub-1A outputs (but recognizing the higher peak currents in the switching paths), tracks rather than zones and thicker copper are generally prefered for these paths. This also applies to the ground pin of U1, which should be tied to the ground plane directly via one or more vias to minimise stray inductance there (rather than tying it to the tab.) Layout issues are a common source of problems in large-current SMPS (and other related applications such as motor controllers).What if instead of tracks I used copper fill zones? Is it better ?
1. Is it a good idea to use Ground copper fill on both sides of the PCB (top and bottom layer)
2. The area i have given for the +12V is too small or big? should i use only traces instead ? Same for +5V/+8V and output pin of the buck converters.
3. Should i use a solid fill or thermal reliefs for the plane copper fill and pads ?
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by Jake Hertz
by Jake Hertz