Can i use a TC1411N for P and N channel mosfets?

Thread Starter

bytraper

Joined Sep 28, 2010
127
Hi Guys,

As usual I am doing most of my learning through you guys (thanks), without all your help and multisim, i would still be working out resistor codes from how to learn electronics type books :)

Anyway, my question is... Can i drive both a N and a P channel mosfet from a single TC1411N driver? It has 2 outputs, the specs of both the P and N channel mosfets are identical. I cant see anything in the datasheet that says I can't, but I just thought I'd double check with people here that may know?

Cheers!
Byt
 

SgtWookie

Joined Jul 17, 2007
22,230
I think that you may have missed this note in the datasheet:
Note: Duplicate pins must be connected
together for proper operation.
So, you need to connect the two OUT pins together.

You really need to use diodes and resistors to the gates of the MOSFETs to ensure that one is OFF before the other is turned OFF. MOSFETs turn off more slowly than they turn on. When both are on simultaneously, you wind up with the dreaded "shoot through", which is a direct short across your supply via your MOSFETs. Besides wasting power, it's very hard on your MOSFETs.
 

Thread Starter

bytraper

Joined Sep 28, 2010
127
Hi guys,
this is what I have so far.

Sarge, you are right, I did miss that, though it didn't seem to stop it working. But good pickup, thanks.



(I've excluded the resistors/diodes for readability so you can easily see what I did). By the way the above example wont actually work as I joined the mosfet legs together, this was just to show what I was thinking.
Is there any advantages from running the P-channel at the bottom?

I'm not so stressed about the p-channel, the driver will open and close the gates very quickly. I'm a little worried about the N-channel. I'm concerned that as the current through it increases the capacitance will rise and make the gate close slower.

Should I maybe run the bottom fets with a pnp/npn driver set-up so that the bottom gate closes faster like the example below? When the power is applied the npn puts power to the gate which opens it, and when the power is off the capacitance holding the gate open drains to ground through the pnp to close it quickly, with the gate of the pnp pulled low by the resistor to ground. I'm not quite sure how to add more dead time to the circuit though....

 
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