Can anyone explain cleary about this project or about this IEEE paper.

Discussion in 'The Projects Forum' started by Thamotharan, Jun 7, 2010.

  1. Thamotharan

    Thread Starter New Member

    Jun 7, 2010
    Wanna know and wanna a clear explaination about this IEEE paper titled "Efficient Implementation of Digital Filters with Use of Advanced Synthesis
    Methods Targeted FPGA Architectures".

    This paper presents an efficient method for
    implementation of digital filters targeted FPGA
    architectures. The traditional approach is based on
    application of general purpose multipliers. However,
    performance of multipliers implemented in FPGA
    architectures does not allow to constructs high
    performance digital filters. In this paper application of
    distributed arithmetic is demonstrated. Since in this
    approach general purpose multipliers are replaced by
    combinational LUT blocks, it is possible to construct
    digital filters of very high performance. However LUT
    blocks can be of considerable size thus advanced
    synthesis methods have to be used to map them efficiently
    into FPGA resources. In this paper an application of the
    functional decomposition based synthesis has been
    investigated. This method is recognised as the best
    synthesis method targeted FPGA architectures and allows
    significant improvements in digital filters implementation.
    The paper presents many examples confirming that
    decomposition allows reduction of logic cell utilisation of
    filter implementation based on distributed arithmetic
    concept with no performance degradation and even​
    increasing it.

    Looking forward for the clear cut explaination. Thanking you in advance.

    Last edited by a moderator: Jun 7, 2010
  2. beenthere

    Retired Moderator

    Apr 20, 2004
    The PDF file attached was an IEEE article that stated "restrictions apply". Those restrictions apply to open publication, as the IEEE requires registration before the material may be viewed.
    Thamotharan likes this.
  3. Papabravo


    Feb 24, 2006
    The article posits a method of replacing the standard Multiply Accumulate method of implementing a digital filter with an equivalent algorithm based on the use of combinatorial look-up tables (LUT). To the extent that the authors have discovered a method that is one to one and onto and does not take NP-time they may be onto something.

    As anybody who has ever worked with any kind of synthesis algorithm will tell you, "if it takes exponential time to compute it ain't worth the powder to blow it away."
    Thamotharan likes this.
  4. Thamotharan

    Thread Starter New Member

    Jun 7, 2010
    Hi Everyone,

    Wat are the necessary things to be known to do this simulation project and Can anyone refer the attached pdf and explain the basic things in it.

    Thank you in Advance.

  5. bertus


    Apr 5, 2008

    The PDF has been removed by beenthere.

  6. Papabravo


    Feb 24, 2006
    Sorry I'm not an IEEE member and don't have access to the paper. A combinatorial lookup table is just a brute force method of enumerating all of the possible inputs, computing the output for each combination of inputs, and then minimizing the resulting Boolean equations.

    The suggestion is that modern synthesis tools can actually do this job in reasonable time. The argument seems plausible.

    Why don't you write to the authors of the paper. They're probably more interested and able to help you then anybody on this forum.