Hi everyone,

My first post here, so I'm trying my best to make it as clear as possible. I've been working on designing a common emitter amplifier, using a small signal model. Attached is the image of the design I'm using.

I currently have the DC gain to my desired value, 500, and everything seems to be going well. Right now I'm using arbitrary values for my capacitors because when doing calculations I think I'm calculating my capacitance values wrong for my desired poles.

I want poles at 100kHz and 400kHz, and I keep trying it but my poles end up in the wrong places on my PSPICE bode plot. I feel like its just something very simple I'm missing. Any help would be greatly appreciated!

The values I'm using, as well as the equation of my common emitter amp are in the attached picture.

 

From your equations, in order for the lowpass pole to be at 400kHz, Cbc would have to be less that 0.5pF, even if Cpi were zero (which it won't be). You will probably not find a discrete BJT with capacitances that are this low.

Have you considered the DC bias conditions, to see if the circuit is practical? If Rc is a passive resistor, you will need Vcc>100V. Not impossible, but definitely unusual.

You are trying to get a gain-bandwidth product of (500*4e3)=2e8. This is impractical in a single BJT amplifier stage.