Two Issues)
Issue the first:
My digital logic assignment asks me to build an 8x1 multiplexer with enable from a 4x1 multiplexer with enable in combination with a dual 4x1 multiplexer with enable, chip.
The first 4x1 was built from scratch (AND, OR and NOT gates only), and works. I've succesfully wired the the inputs to one of the 4x1's on the dual chip so that it works as well. Now, I need to add these two output values together (and I am not allowed to use any additional gates), meaning I must use the second half of the dual 4x1 chip.
I didn't think this would be too troublesome, as the original 4x1 was made from scratch and I could map out the gates, however, I can't seem to make this click. I'm attempting to use the OR gate at the end of the 4x1 within the dual chip to add my values together, doubling up my inputs so that they are added or multiplied to theirselves until they reach this crucial or gate. Also, the enable and select lines have been attached to this multiplexer as they have been to the others, working ones (the enable for the second successful working mux being C', the third select, or course).
So, my inputs for my the third mux are:
mux1out to I0
mux1out to I1
mux2out to I2
mux3out to I3
I can't seem to get anything but 0 as the final output.
Second Issue:
Using a 2x4 binary decoder with enable, built from scratch, along with a a dual 2x4 decoder with enable chip and one inverter, build a 3x8 decoder with enable. I know the 2x4 decoder built from scratch works.
I have my inverter coming off my C select line, which I am using for the enables on the dual decoder chip (one enable gets C', the other igets C).
I get the feeling that I should be feeding the four outputs from my working decoder into the inputs of the dual decoder chip (two a piece), but I can't really find a reason to back up this hunch. Any hints on why I should do this (or contrary advice, if I'm going in completely the wrong direction) would be greatly appreciated.
Thanks for reading,
-J
Issue the first:
My digital logic assignment asks me to build an 8x1 multiplexer with enable from a 4x1 multiplexer with enable in combination with a dual 4x1 multiplexer with enable, chip.
The first 4x1 was built from scratch (AND, OR and NOT gates only), and works. I've succesfully wired the the inputs to one of the 4x1's on the dual chip so that it works as well. Now, I need to add these two output values together (and I am not allowed to use any additional gates), meaning I must use the second half of the dual 4x1 chip.
I didn't think this would be too troublesome, as the original 4x1 was made from scratch and I could map out the gates, however, I can't seem to make this click. I'm attempting to use the OR gate at the end of the 4x1 within the dual chip to add my values together, doubling up my inputs so that they are added or multiplied to theirselves until they reach this crucial or gate. Also, the enable and select lines have been attached to this multiplexer as they have been to the others, working ones (the enable for the second successful working mux being C', the third select, or course).
So, my inputs for my the third mux are:
mux1out to I0
mux1out to I1
mux2out to I2
mux3out to I3
I can't seem to get anything but 0 as the final output.
Second Issue:
Using a 2x4 binary decoder with enable, built from scratch, along with a a dual 2x4 decoder with enable chip and one inverter, build a 3x8 decoder with enable. I know the 2x4 decoder built from scratch works.
I have my inverter coming off my C select line, which I am using for the enables on the dual decoder chip (one enable gets C', the other igets C).
I get the feeling that I should be feeding the four outputs from my working decoder into the inputs of the dual decoder chip (two a piece), but I can't really find a reason to back up this hunch. Any hints on why I should do this (or contrary advice, if I'm going in completely the wrong direction) would be greatly appreciated.
Thanks for reading,
-J
