Im using a buffer in a FPGA digital design package and I was wondering if I pass a single HI bit through it for an instant during communications will that HI remain on the line after the buffer (controling address lines in multiplexer if I send 11 i need it to remain on the address lines.) If not what could i use maybe a T-flipflop???

Thank you

 

A buffer by definition will follow its input after a small propagation delay on the order of several hundred picoseconds to several nanoseconds depending on the voltage and the technology you are using.

 

Buffer with a latch, sometimes called a bus buffer can be set with an input then locked so that the output will not change until you tell it to.

Note that there are two different parts in here, they differ based on whether control is active high or active low.
http://delta.octopart.com/Texas_Instruments__SN74LS126AN.pdf
It's obsolete but...
http://alpha.octopart.com/Texas_Instruments__SN74HCT573N.pdf
http://beta.octopart.com/Texas_Instruments__SN74HC373DW.pdf
etc are not.

You'll have to match such a part to what you need to do. You could stuff this inside the FPGA if there is room.


Use http://www.octopart.com and search as there are many varieties.
http://octopart.com/search?q=latching+buffer