Hi everybody!!!

I am currently on my thesis and I am implementing a boost converter.
The following schematic "Boost Converter.png" shows exactly what I want to do.

The driver circuits that I use have an on-voltage of 12Volts and an off-voltage of -9V.

My question is about the picture "TEK005.jpg" I took from the oscilloscope. The "blue" signal is the signal at the gates of Mosfets T1 and T2 (parallel connected). The "green" signal is the signal at the gates of Mosfets T3 and T4 (parallel connected).
I am trying to understand why does the voltage at gate of Mosfet T1 and T2 rise the moment that the voltage at gate of Mosfet T3 and T4 normally rises according to the control signal (orange).

Thank you in advance for your help!

 

Well, we're not seeing some things we'd like to see; like a board layout, how long your interconnecting wires are, actual component values, how you are actually driving the gates... things like that.
You have "N_MOSFET" for values instead of the actual part numbers.
You have ETD54 for the inductor; that's just a basic Ferroxcube part number, but you left out the inductance of it, or at least specify AL and number of turns.
Datasheet: http://www.ferroxcube.com/prod/assets/etd54.pdf

However, you probably have some capacitive coupling between your drain and gate. There's a Qgd specification in the datasheet.

 

Thanks a lot in advance!!!

Well, we're not seeing some things we'd like to see; like a board layout, how long your interconnecting wires are, actual component values, how you are actually driving the gates... things like that.

You were right!!! I believe now it's a little better...

About the driver circuit:
I am using the ACNW3130 MOSFET driver with optocoupler. The on-state voltage at the gate is 12 Volt and the off-state -9V.
The driver circuit is connected to the main board of the boost converter vertically through the pin headers. The length of the wire from the gate resistor, which is on the driver circuit to the gates of the MOSFETs is about 3 cm.

However, you probably have some capacitive coupling between your drain and gate. There's a Qgd specification in the datasheet.

What I know about the parallel connection of MOSFETs is that their layout should be symmetrical and I tried to do that as far as I could... but your notice that the gate inputs are highy capacitive and the stray inductances can cause unwated high-frequency oscillations. This explains the oscillations that I see when the MOSFETs T1 and T2 are going to the on-state. But, what about the strange behaviour of the voltage at the gate of MOSFETs T1 and T2, the moment that the MOSFETs T3 and T4 are going to the on-state?

 

Will you attach your Eagle .sch and .brd files?
Having the images is good, but there is no scale defined. Having the original BRD/SCH files available simplifies things.

 

Will you attach your Eagle .sch and .brd files?
Having the images is good, but there is no scale defined. Having the original BRD/SCH files available simplifies things.

These are the schematic and board of the boost converter and its driver circuit!!!

 

But, what about the strange behaviour of the voltage at the gate of MOSFETs T1 and T2, the moment that the MOSFETs T3 and T4 are going to the on-state?

I think I found it...The drain-source voltage of MOSFETs T3 and T4 rises with a very high dv/dt slope. This voltage rise is capacitively coupled into the gate thru the gate-drain capacitor, Cgd, resulting in an induced voltage
at the gate of the MOSFETs T1 and T2.

http://www.irf.com/technical-info/whitepaper/cipl_apec04.pdf

What is your opinion?

I really thank you in advance for the triggering thought of yours!!!

 

You have errors in both schematics, which have lead to inconsistencies between the boards and the schematics. There are parts on the boards which are not in the schematics. This causes a great deal of trouble when attempting to reconcile the two. Your life will be unpleasant until you get rid of the inconsistencies.

Always add parts via the schematic, not the board. Always use Erc before creating a board. Use Erc early, and use it often. The happier you keep Erc, the more pleasant your life will be.

You have a lot of errors that were caused by using NAME on wires to indicate pins, but then connecting the wires to supply symbols. As a result, you have conflicting NAMEs assigned to nodes. Eagle will not be happy about this at all. You could make the pins visible instead, or use the Text tool and place text next to the parts if needed.

You're using the "0v" symbol instead of the GND symbol. I really like using GND instead, as GND implies the 0v reference, and is much more commonly used.

You have text overlapping wires/vice versa. This makes the text hard to read.

I'm sorry it's taking me awhile to get to you, but there are a number of folks with questions and doesn't seem like many handing out answers this morning.