Block diagram for modem?

Thread Starter


Joined May 6, 2008
Hi, I'm just going to quote the whole word problem b/c I don't fully understand it. (Figure 2 is a parallel-in, serial-out shift register w/ a series of and/or/inverter gates that are used to establish preset and clear conditions when the "load" signal is activated)

"A circuit like the one in Fig. 2 is used in modems to convert an 8 bit byte into a serial stream of information. In order for the circuit in Fig. 2 to operate, it must continually get loaded with a byte and serially transmit that byte out. Several additional circuits are required, including
1) a circuit to load the next byte into the parallel to serial converter after the last byte had been transmitted out.
2) a circuit that will stop transmission if a problem occurs.
3) a circuit to generate a clock signal.

Propose a block diagram that will provide these functions."

For the first part, I was thinking about using a JK FF but I have no idea how to make it send out the last byte before the next one is loaded in.

For part 2, I have no idea how to make it stop when a problem occurs, any tips or devices I should use?

For 3 I was just going to add a neg. edge triggered FF, but don't really understand what is needed to generate a clock signal, one was just presented to us usually.

I am somewhat lost here and could really use any help.
Thank you!


Joined Feb 24, 2006
The short answer is divide and conquor.

Let's start with number 3. A clock signal for a logic curcuit comes from a device that can generate a stable periodic signal. This is not strictly a logic function, it ventures a bit into the analog domain. Terms you might want to Google include "astable" and "multivibrator". It is often the case that the frequency of a clock is controlled by a quartz crystal. Perhaps the simplest kind of oscillator you can build from a CMOS inverter is the relaxation oscillator. It takes one inverter, one resistor, and one capacitor. It's not very stable but it will generate a square wave.

Part 2 Let's leave this one alone until we get something working so we have some idea of exactly what can go wrong and how we might detect that situation.

This brings us back to part 1. Let's try to get an intuitive grasp of the obvious.
  1. You can't load the shift register while it is shifting.
  2. You need to have a piece of data ready to go.
  3. The serial output can't tell the difference between a "shift" and a "load". There is a time when it changes and there is a time when it is stable.
  4. You need to "count" the things(bits) you are handling
Keeping those four things in mind, do any ideas come into your head?

Final HINT: Google "Finite State Machine"

Thread Starter


Joined May 6, 2008
So, would it be a better idea to use Data FF's?
We haven't done the concept of a finite state machine yet, I'm just wondering how to hook a clock up to it. Also, if I were to replace the Q's with D FF's would that work?

I understand what to use to make a clock now, thanks you!
Any further help would be appreciated.