BJT transistor - CE amplifier design

Discussion in 'Homework Help' started by Sharpiedeluxe, Apr 1, 2010.

  1. Sharpiedeluxe

    Thread Starter New Member

    Apr 1, 2010
    So, I'm trying to design a BJT amplifier to meet some specified requirements. The amplifier should remain in the active region. I want to get a gain of "4", and also have my Voltage output swing to be 6Vpp. The restrictions are that the input impedance must be a minimum of 15kohms, and the output impedance must be no greater than 5kohms. I'm given that I have a supply voltage of 16V, Beta falls in the region of anywhere from 80<->250, and the transistor has a Vbe(active) of 0.7V, Vce(sat) of 0.2V. Vt = 25mV.

    For this, I thought about starting off by choosing a CE amplifier with an Reu to meet the requirements (i'm guessing). I'm not exactly sure how to start, but what I did do was try to relate the swing and gain considerations into a single equation.

    I did a DC bias from the collector to emitter:
    16v = B*Ib*Rc + Vbe(act) + Ib*Rb ; to get an equation for Ib

    then I believe that the symmetrical swing should look like:
    6Vpp = Ic * Rc (where Ic = Ib * B)

    I used the hybrid-pi model for the ac bias.

    For the gain:
    gain = (vout/vin) and for the common emitter in this scenario, I think that the equation simplifies to:
    4 = -(B * Rc) / [(B + 1)*Reu + R(pi)]

    doing the ac bias, Rin = R(pi) + (1 + B)Reu
    and Rout = Rc

    With this, I think I should be able to choose worst case minimums and maximums for Beta and Rout, and solve for what Rin would be. I hope I'm making sense. Please tell me what you think, or if I'm on the right track or not (X_X) thanks!

    Also, honestly, I don't really know what to do with RL or Rs or if they matter for this design. How would they affect my calculations? :confused:
  2. jlcstrat

    Active Member

    Jun 19, 2009
    RL and RS will only affect the AC design
  3. hobbyist

    AAC Fanatic!

    Aug 10, 2008
    I would like to compliment you on the very excellent work you did thus far, you show a lot of potential to want to learn this and the tremendous effort put forth, this is a good example of how people in the "homework forum", should post there requests.

    I didn't have time to look over and check your calculations, but just wanted to compliment you on a fine job, in posting your request...
  4. Sharpiedeluxe

    Thread Starter New Member

    Apr 1, 2010
    Thank you very much! Yes, I indeed do want to learn this material, it's very challenging for me, but I'm sure if I put time into it then it'll pay off. :)
  5. PRS

    Well-Known Member

    Aug 24, 2008
    Here you need to determine V_c since it will be the dc bias upon which the signal rises and falls. Use 2V_{CE} or 2I_CR_C whichever is smaller. This comes about because the signal needs to swing 3 volts upward and 3 volts downward from that center point. This happens within a window created by Vcc and Ve.

    This is easily acheived by the design having an unbypassed emitter resistor. It reflects through the emitter to the base by a factor of Beta. As for Rout, it is basically Rc.

    All of this is consistent with the 2N3904. The Beta condition can be coped with because of your unbypassed emitter resistor. More on this later.

    I don't see this equation following a genuine path from the 16 volt source to ground. It goes against the current through the emitter base junction. A better way is to thevinize the input and do a KVL around the path leading to an equation for Ie. This is the standard way.

    No, this is not right, revealing, I think, confusion on your part. Stay with me; we'll clear it up. This tells me I have to do some drawing with Paint.


    This doesn't look right. The gain is the resistance at the collector divided by the resistance at the emitter. Chew on that and I'll help you out if you don't get it.

    You forgot the parallel combination of the base bias resisters. And I've always used Beta*Reu.

    Yes, except slightly modified by 100kohm of collector output resistance. I don't know how strict your teacher is, but I'd include it for good measure.

    If your instructor did not specify Rs or Rout I don't think we need to worry about them. To be sure you might ask him or her.

    Good luck! ;)
  6. PRS

    Well-Known Member

    Aug 24, 2008
    Here's my solution to the problem. See the attached photo. It was drawn and tested with LTSpice. So we know it works and I'm not just blowing hot air.

    Here's how I went about designing it. The first concern was figuring out Vc and Ve so the signal would swing plus and minus 3 volts. The maximum available voltage is 16 volts so that's the top of the sine wave, but here's a trick: always design for more than you need; that way any changes due to 10 percent resistors are of no significance.

    Vc needs to be Vcc - 3 volts but let's make it 4 for a little overkill. Thus Vc is about 12 volts.

    Next, the lower part of the signal swings down to Ve and Vce(sat) = .2 volts. We can here again use a little overkill. Instead of Ve = 12 - .2 -3 volts for a bare fit, let's make the whole drop 4 volts. So Ve = Vc - 4 = 8 volts.

    I always think 1 mA when it comes to the current. Using more or less is possible, but complications can come up. So 1 mA it is.

    For Ie to be 1mA while Ve is 8 volts, we need 8k at the emitter. For a gain of 4 we need Rc to be higher than Re1 by a factor of 4. The design specs want Rout < 5k so let's make it 4. That means Re1 is 1k and that means Re2 is 7k.

    Now for the base bias resistors. They need to be large because the design spec is at least 15k input resistance. The high input resistance of the device makes the discovery of suitable Rb1 and Rb2 a matter of simple voltage division. That is, Ib is only about .01mA if Beta is 100.

    We could make these base resistors very large, but that would make the circuit dependent on the value of Beta. A standard way of resolving this is to make the current in the divider be 10 times less than the current in the emitter. Thus .1 mA.

    So 16/(R1+R2)=.1mA means R1 + R2 = 160k.

    The base voltage needs to be 8.7 volts because of the .7 volt drop across the base emitter junction where we want 8 volts.

    So (R2/160k)*16 = 8, from which R2 = 87k and R1 = 73k

    But let's use standard values and let
    R1 = 68k and R2 = 82k.

    You can put these values into the equations above and see they work out to a base voltage of 8.75 volts, which is close enough.

    Did we meet all the specs is the question now?

    Rin = the parallel combination of R1 and R2 which are in turn in parallel with the transistor's input resistance. This is Re1 reflected through the emitter to the base by a factor of Beta, which for Beta=100 is about 27k, so we succeeded here.

    Rout = Rc in parallel with the transistor's output resistance (about 100k) thus Rout is a little less than 4k.

    The gain is given by Av = the resistance seen at the collector (I ignored the load resistor since it wasn't specified. I just made it really large for spice to look at) divided by the AC resistance at the emitter which is just Re1 + re and re=Vt/Ie is about 25 ohms. So we got our gain. If it needs to be exact put a 1k pot in place of Re1.

    Finally, the spice output shows a 6 volt peak to peak swing.

    I hope you study this. Good luck. Your teacher may wish more exact equations. In that case thevinize the input and do a loop around the emitter resistors. Don't forget Vbe when you do this.

    Using this equation you get Ie. If you need to prove your design is truely independent of Beta, solve for Ie (using thevenin) and substitute the extreme values into the equation showing a small percentage of difference.
    Last edited: Apr 2, 2010
  7. Sharpiedeluxe

    Thread Starter New Member

    Apr 1, 2010
    Thank you guys very much, I read through it all, and I see where I made huge mistakes! I actually talked with my professor today and he directed me towards the same method that you guys used for solving this. I haven't yet been able to accomplish this with my calculations, but I'll keep trying, thanks again for all your hard work!