I have an application where I need to take two 0 - 3.3V pulses from an FPGA and combine them to produce a Vout which can swing from -15v to +15v.

Here are some requirements and specs

• The max switching speed is 1Mhz @ 25% duty cycle
• The 3.3v pulses from the FPGA must go into an optocoupler to isolate the sensitive FPGA from the higher voltages
• The load to this circuit will be a 75 Ohm cable that is transformer coupled
• I will have a total of 4 of these 2-input channels

I've included some images below to best explain what I'm trying to do. I'm wondering what type of circuit is recommended?

I should note that we had a few microchip TC4432 MOSFET drivers lying around and I used a pair of those, one for each input to directly drive each side of the transformer and it seemed to work. However, I'm fairly sure MOSFET drivers are not intended to source/sink a constant amount of current (~250mA in my case) but rather have short peak currents to charge up the gate of a FET; am I correct?

The other alternative I can think of is a full-bridge motor driver but I'm not real sure how to set that up.

Thanks!

Two examples of what the input -> output relationship looks like

What goes in the black box?

 

Hi SiegeX1,


Questions:

1. What is your application?
2. Is this going to be a data line using AMI encoding?
3. How long is the coax line?
4. The transformer offers isolation, so why is the opto-coupler needed?
5. You could use a class B push-pull driver if the transformer primary was center-tapped. Can you get a center-tapped transformer?

15V into 75Ω at 25% duty cycle is 15/75 = 0.2A * 15 = 3Watts * .25 = 0.75 Watts. 10% of this would be dissipated in the TC 3144 (75mW). The TC3144 has a θja of 155 °C/W for the SOIC package, therefore the junction temperature would rise to 155 * .075 = 11.6 °C above ambient with the worst case data pattern of all ones. No problem there.

A continuous maximum current spec is missing since it is unimportant for most MOSFET drive applications. You require a 200mA drive that lasts for 250nS. The spec only mentions a 100mA test condition for the output level test, and a 3A pulse into a capacitive load for 25nS. Therefore you can't be sure that 0.2 Amp won't cause a failure later in life. My guess is that it would not be a problem for a hobby project.

The TC3144 output Z is 7 to 10Ω which is a significant part of the line Z. Depending on your requirements, this may, or may not be important.

Regards, Ifixit

 

Hi SiegeX1,


Questions:

1. What is your application?
   This will be a digital protocol simulator to help in verification/validation testing. I wrote the FPGA code and now I need to condition the signals to match that of the various encoding schemes we use
2. Is this going to be a data line using AMI encoding?
   I was not familiar with the 'AMI' term but after looking at wikipedia, yes that is what we use although we call it 'Bi-polar'. We will also do 'Uni-polar' encoding which is what my top input/output example shows. The bottom example is the AMI or bi-polar encoding as you mentioned.
   
3. How long is the coax line?
   I believe it would be no longer then ~10ft or so
4. The transformer offers isolation, so why is the opto-coupler needed?
   Perhaps this is overkill but I was worried about directly connecting the FPGA to an IC with source voltages in the 15-18V range. If for some reason the MOSFET driver fails I'd rather blow a $0.50 optocoupler than an expensive FPGA
5. You could use a class B push-pull driver if the transformer primary was center-tapped. Can you get a center-tapped transformer?
   Yes, that should be no problem. How would this circuit look? Is it as simple as grounding the center tap and then have two AC-coupled drivers, one each on the high and low sides of the primary? My gut feeling is that it's a bit more complicated than that.

15V into 75Ω at 25% duty cycle is 15/75 = 0.2A * 15 = 3Watts * .25 = 0.75 Watts. 10% of this would be dissipated in the TC 3144 (75mW). The TC3144 has a θja of 155 °C/W for the SOIC package, therefore the junction temperature would rise to 155 * .075 = 11.6 °C above ambient with the worst case data pattern of all ones. No problem there.
I follow all your calculations except for the 10% dissipation figure; what did you use to calculate this?

A continuous maximum current spec is missing since it is unimportant for most MOSFET drive applications. You require a 200mA drive that lasts for 250nS. The spec only mentions a 100mA test condition for the output level test, and a 3A pulse into a capacitive load for 25nS. Therefore you can't be sure that 0.2 Amp won't cause a failure later in life. My guess is that it would not be a problem for a hobby project.
Perhaps this is not the right IC/circuit as this needs to be more robust than a hobby project.

The TC3144 output Z is 7 to 10Ω which is a significant part of the line Z. Depending on your requirements, this may, or may not be important.
In regards to output resistance. In the circuit I setup where are two of these MOSFET drivers, each one tied to one of the coupling capacitors. Does that mean there is a total of 10+10+75=95Ohm for a real drive of 157mA with a 15V 'on' voltage? If so that means each 10ohm drops 1.57V so there is only a 11.86V drop across the 75ohm load. How correct is this observation?

Regards, Ifixit

Also, the spec talks about the ability to take up to 300mA into one of its outputs without latchup. I'm fairly sure that the configuration I have them means when one driver is sourcing, the other is sinking through its output. Since my drive is 200mA (or is it 157mA?) I should be OK. However, where I am confused is that note 3.5 says that pin 6, the sink output, can sink up to 1.5A of peak current. So in what situation is 300mA the limit, and what situation is 1.5A the limit?

Thanks so much for your help and enlightenment

 

Hi SiegeX1,

1. In this case you should design to be quite accurate with respect to pulse shape, level, width, and spacing to the next pulse. After all you don't want to fail tests because your test signal is inconsistant.
2. Okay.
3. Good. Transmission line effects will be minimal.
4. You'll need a fast one that can handle 15V. Tprop = 10nS or less. Similar rise and fall times etc. Perhapes another transformer would be better, or change the one you have to have a 1 to 3 turns ratio. Of course, the primary current will be 3 times higher. How about a zener clamp on the FPGA outputs to ensure 15V feedback due to a failure doesn't damage the FPGA.
5. See the attached figure. You could use your TC4432 to drive the MOSFETs. This is just an example circuit. The MOSFETs should be better choices that have much lower on resistance specs.

I follow all your calculations except for the 10% dissipation figure; what did you use to calculate this?

This is based on the spec saying that the driver Z is 7 to 10 ohms, which is approximately 10% of 75Ω.

Since the transmission line is short, the terminating impedances are less important and can be adjusted to suit with resistors if needed.

The 1.5A spec is the current the TC4432 can drive to charge the gate so it is a very short duration.

Latch-up refers to a situation where the inputs, or outputs of a device are driven beyond the rail voltage there-by causing current flow and possible invalid states because the device is driven beyond its limits. The TC4432 can handle 300mA before this can happen. This should not be a problem for your application. You should not use it as the main driver anyway.

I won't be available for the next week (off to Vegas Monday), but there are lots of people on the forum that can help.

Regards,
Ifixit

 

Thanks so much for the thoughtful post, I really appreciate the help. I'm actually going to Tahoe all next week so perfect timing =).

In the mean time, your circuit sparked a few questions for me, no rush on the answers.

1. What purpose does the parallel RC circuit serve? I ran your circuit through LTSpice and I seemed to get (nearly?) identical output with or without the RC circuit in place. I know the 1nF cap is a very low impedance to the ~1Mhz pulse (~16mOhm), but why the 100 Ohm resistor?
2. Your pulse stimuli go from 0-10V but my FPGA only does 0-3.3V. I simulated what Vout would look like at at 0-3.3V input pulse to the MOSFET gate and it didn't look good at all. I'm guessing this means I wasn't driving Vgs hard enough to put it into saturation?
3. Because of #2 above, would the two pulse stimuli actually be high-side MOSFET drivers in my real-world circuit, and my FPGA connects to said drivers? If so, why is it better to use external discrete transistors driven by MOSFET drivers vs having the MOSFET drivers provide the drive across the transformer?
4. Do I need to worry about Back EMF at all? I've looked at a few relay circuits where a diode is put across the coil in a normally reversed-biased configuration. Because the center tap is held at a rail voltage, do I not need to be concerned about this?

Thanks so much. Have fun in Vegas!

 

Hi again,

So I did some research on some parts and I came across the Si8235 which is a dual MOSFET driver that has isolated inputs. It can handle up to 4A peak current and switching speeds up to 8Mhz (I only need 80Khz -> 1Mhz).

I wanted to design a pretty generic driver board that can support a wide range of Vdd voltage as well as have the option of running in a non-isolation mode if deemed sufficient. The way I handled this option was via a 4PDT switch which when in the SET=0 configuration would tap the Vdd line through a 5V LDO regulator and route that and its associated GND to the Si8235's normally isolated 5V 'VDDI' and 'GNDI' pins. In this way you are sacrificing isolation for the benefit of only needing to provide one voltage source (Vdd). When in the SET=1 configuration, isolation would be enabled by routing a separate 5V source and associated GND. The other two poles of the switch in this mode are for disabling the LDO regulator and turning on an LED to indicate isolation is in use.

Since there wasn't a SPICE model for the Si8235 (nor would I know how to import it into LTSPICE if there were), I simulated its functionality by the use of a couple of optocouplers and some Linear High-Side/Low-Side MOSFET drivers of which I only use the low-side. I had to simulate at a much slower frequency, ~40Khz, because the optocouplers couldn't keep up with the 1Mhz switching speed even though the Linear MOSFET driver had no problem. I also put a Voffset on the D0 and D1 lines to show that the isolation was working correctly.

I would really appreciate a critique of my design for possible improvements and/or errors or oversights. Also, I have the following questions that I would appreciate some insight into:

1. Without the two 75 ohm resistors between each of the two primaries, I was getting quite a bit of ringing even though the load end was terminated correctly based upon a transmission line with Z0 = 75 ohm. As I mentioned earlier, I'd like to make this design fairly generic so is there a better way/place to terminate than what I did? Is the only/best way to support a range of loads by using potentiometers in place of the fixed 75 ohm resistors?
2. What criteria should I look at for deciding how much inductance to use for the transformer when dealing with pulses? I pretty much randomly chose 5mH and it seemed to work just fine for my range of frequencies (80Khz -- 1Mhz) but I don't have a real feel for how the inductance is influencing the pulses and if there is an optimal value.
3. Since I want a 1:1 ratio between input/output pulses across the transformer, do I need to get a 2:1 transformer with a center tap to maintain a unity voltage gain?
4. Whilst searching for a MOSFET to use, I noticed there are two load ratings. One is gate charge 'QG' and the other is Input Capacitance 'Ciss'. Choosing an NMOS model in LTSPICE only shows gate charge. However, the Si8235 datasheet has an excel graph towards the end which gives max load, CL, vs frequency. At ~1Mhz, the max CL I can drive is roughly 1nF. Now the question is, is this CL the Ciss figure? How does Qg relate to Ciss? Can you calc one from the other?
5. Is my design of using a 4.7V zener in conjunction with the LED to support a wide range of Vdd voltages a sound one? I believe I calculated that Vdd could go up to ~26V before the zener current nears its 70mA maximum. This voltage is right inline with the max voltage for the Si8235

Thanks all

 

Hi SiegeX1,


Re: post #5…

• Yah, the simulation will work well without them, but in the real world you may need the resistor to suppress ringing at the gate due to parasitic effects in the layout. Keep rising and falling edges only at fast as needed.
• 3.3V is not enough for this application, however, 10V is more than you need since your maximum drain current is only 200mA (15V/75ohm). The small the mosfet, the smaller the gate-charge you’ll have to drive.
• You don’t need high-side drivers for this application using a center-tapped transformer. That’s one of the benefits of the CT.
• No. Another benefit of the CT transformer, the EMF of one side is absorbed by the other.

Re post #6…

“So I did some research on some parts and I came across the Si8235 which is a dual MOSFET driver that has isolated inputs. It can handle up to 4A peak current and switching speeds up to 8Mhz (I only need 80Khz -> 1Mhz).”


What is the worst case pulse level required? 15V into 75ohm? If so, you only need to select a small MOSFET with a 1A max Id spec. Its gate charge requirements will be easier to handle.

“I wanted to design a pretty generic driver board that can support a wide range of Vdd voltage as well as have the option of running in a non-isolation mode if deemed sufficient. The way I handled this option was via a 4PDT switch which when in the SET=0 configuration would tap the Vdd line through a 5V LDO regulator and route that and its associated GND to the Si8235's normally isolated 5V 'VDDI' and 'GNDI' pins. In this way you are sacrificing isolation for the benefit of only needing to provide one voltage source (Vdd). When in the SET=1 configuration, isolation would be enabled by routing a separate 5V source and associated GND. The other two poles of the switch in this mode are for disabling the LDO regulator and turning on an LED to indicate isolation is in use.”


This is not required since the VDDi of a real Si8235 is always isolated.

“Since there wasn't a SPICE model for the Si8235 (nor would I know how to import it into LTSPICE if there were), I simulated its functionality by the use of a couple of optocouplers and some Linear High-Side/Low-Side MOSFET drivers of which I only use the low-side. I had to simulate at a much slower frequency, ~40Khz, because the optocouplers couldn't keep up with the 1Mhz switching speed even though the Linear MOSFET driver had no problem. I also put a Voffset on the D0 and D1 lines to show that the isolation was working correctly.”


Meticulous.

“I would really appreciate a critique of my design for possible improvements and/or errors or oversights. Also, I have the following questions that I would appreciate some insight into:”

• What I posted was not intended to drive a transmission line, but rather a “lumped” impedance load of 75ohms. This gets you a 15V pulse into a 75 load driven from a 15V supply. If you are going to drive a terminated transmission line then put a 75 resistor in series with the primary inputs. Of course the pulse level will be reduced by half. To compensate, use a 1:2 ratio transformer, or a 30V supply.
• This is somewhat arbitrary, but you should choose only enough inductance to do the job satisfactorily. Not enough will cause the top of your pulses to droop and too much lowers the self-resonance point by increasing the inter-winding capacitance, also the cost and size are higher. 1mH would likely work okay as well for this application.
• Yes. Why do you need 1:1? What is the maximum output pulse height you need?
• Design using the gate charge spec. Gate charge takes into consideration the capacitance from gate to source and from gate to drain. This is complex because as Vg rises, Vd is falling, dumping its charge into the gate, which tends to turn it off again. Using the gate charge spec for fast switching applications simplifies calculating the drive level needed to get a switching time required. Drive current = gate chg (Qg) in nano-coulombs (nC) / rise time required (nS) e.g. if a mosfet has a Qg of 15 nC and you require a rise time of 25nS then 15/25=0.6 Amps.
• In my opinion you don’t need isolation at all, but if you use the Si8235 then you certainly don’t need to isolate the VDDI, just use the same supply as the FPGA uses.

P.S. Had a great time in Vegas, only lost $4 to the one-armed bandits.

Regards,
Ifixit

 

Hi again! Sorry for the late reply, I was on travel for the last few days.

What is the worst case pulse level required? 15V into 75ohm? If so, you only need to select a small MOSFET with a 1A max Id spec. Its gate charge requirements will be easier to handle.

Yes, I was able to get a hard copy of the requirments and at ~1Mhz the requirement is to have a pulse amplitude between 9V and 15V across a load that has 75ohm in parallel with a 5mH inductor (see attachment)

In regards to the transformer, I'm having an awful hard time trying to wrap my head around what I really need in order to get a +/-15V pulse on the output using a +15V source. I started a separate thread regarding my troubles getting my head around modeling it. Would appreciate it if you could take a look at that as well.

Also, thanks for clearing up the gate charge vs gate capacitance. I found a really nice white paper by microchip that went into quite a bit of detail and now I feel I have a pretty strong grasp of what's going on.

P.S. Even though you nearly broke even, you still came home a winner because those new video slots with all the bonus levels have quite a bit of entertainment value