# BCDCounter for 0 to 9

Discussion in 'Homework Help' started by Cheezy, Jan 22, 2013.

1. ### Cheezy Thread Starter New Member

Jan 22, 2013
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I was told to do a BCDCounter for 0 to 9 and after 9 it will reset and start over from 0 again. No reset switch are allowed and resetting should be done in the circuit without using a switch as reset. I don't understand which part I had done wrong and just couldn't get the 7 segment display to even display the numbers.

Did I connect something wrongly??? Help would be appreciated

2. ### t06afre AAC Fanatic!

May 11, 2009
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1,227
Without knowing your assignment. I think your teacher want you to build a four bit synchronous counter. I suggest some use of Google here if you you need info. Designing a four bit synchronous counter. Is the ultimate Karnaugh map exercise

3. ### ScottWang Moderator

Aug 23, 2012
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991
Does your 7 segment display including a bcd to 7 segment decoder ?
If the answer is no, then you need one.

4. ### absf Senior Member

Dec 29, 2010
1,867
510
The "RESET" of your JK F/F 7476 is active low. You either need a 4-input NAND for your U7 or add an inverter gate on the output of 7421.

Your BCD counter would only count 0-8 and resets on binary 9 or "1001" binary.

Allen

5. ### absf Senior Member

Dec 29, 2010
1,867
510
Here is how it was simulated in proteus..

You may also save 2 inverter gates by using the /Q output of the 7476. But I dont know if it would affect the timing of the circuit.

• ###### 7476 BCD.PNG
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Last edited: Jan 22, 2013
6. ### Cheezy Thread Starter New Member

Jan 22, 2013
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My JK flip flop contains P and C as you can see , differs a little from ur diagram but is it the same as S and R in ur diagram? Timing of the circuit is affected by the clock rate so I think its possible for me to set the rate to 1Hz. And ur diagram seems very similar to mine just that I have the L1 on the right side of my diagram , which seems that I could add it to your diagram after the INVERTER NOT back to U1:A

7. ### WBahn Moderator

Mar 31, 2012
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There are a few issues with this circuit -- not all of which may show up in simulation.

You are decoding four signals looking for a match to a particular pattern and, if that pattern is seen, you perform an asynchronous reset of the circuit.

In general (say this was a synchronous counter, other than the reset part), the outputs can change in any order.

So, for instance, when it goes from 7 to 8 it could go

0111 -> 1111 -> 1011 -> 1001 -> 1000

And you could see a decoding glitch that is long enough to reset the circuit.

Since this is a ripple counter, you will see it go

0111 -> 0110 -> 0100 -> 0000 -> 1000

Next, because you are resetting as soon as you see 1001 (and let's assume you don't have any decoder glitch issues), then your counter will just barely enter 1001 and immediately reset to 0000. This will happen so fast that you won't notice the '9' on the display at all and it will look like it went from '8' to '0' (as a previous response noted).

Finally, and this is why you aren't seeing anything happening, is that your reset inputs are active-LO and your AND gate produces a LO signal (and hence resets the counter) in every state OTHER than state 1001 (as a previous response noted).

absf likes this.
8. ### Cheezy Thread Starter New Member

Jan 22, 2013
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I manage to get the circuit to run from 0 to 9 and reset but I still don't quite understand , you can see that i invert the first and third JK flip flop so they can become 0s later. But I still don't understand what exactly i'm doing.

Can someone explain to me what exactly did i do? I get the answer but I don't understand why I manage to get the answer.

Last edited: Jan 25, 2013
9. ### thatoneguy AAC Fanatic!

Feb 19, 2009
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If you disconnect your NAND reset, does it get to 9?

Did you see the post above yours by WBahn?

10. ### WBahn Moderator

Mar 31, 2012
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For the most part, you did what we told you needed to be done. You inverted the AND output because the reset is active-LO and you wait until you see state 1010 (i.e., 10 or 'A' in hex) to reset so that you get to actually see state 1001 (9).

This is essentially what is happening to your counter state as you approach reset:

777777777788888888889999999999A0000000001111...

Before, what you were seeing was more like

7777777777888888888890000000001111111111222...

As you enter the state that you have decoded, you only stay in that state long enough for the AND gate to assert its output, the inverter to invert it, and the reset inputs of the flip flops to act on it. With today's ICs, that whole process probably takes a fraction of a microsecond.

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