Sadly, your not correct here. The bit line is where you both input data and read data from. The word line selects the RAM element you wish to write to or read from.thanks for the idea, i appreciate a lot. let me see if i understood it well. so, the bitline is where you input data (through the nMOS gate) and the wordline is accessed through the nMOS drain? please explain further if i didn't get it right. i'm new to memory circuits. tnx
When Vgs > Vth for the nMOS transistor, the transistor channel has an inversion layer (i.e. we say the transistor is open) and current flows from drain to source and the capacitor begins to charge up from the bit-line.Dave,
for sequence #3,
3. When Vgs > Vth for the nMOS transistor the transistor opens and the capacitor begins to charge up from the bit-line.
should this be:
3. When Vgs > Vth for the nMOS transistor the transistor close (current flows from drain to source) and the capacitor begins to charge up from the bit-line.
if that is the case, then i already understood it. please confirm
Glad to be of help, any further problems let us know and we can try and help you out.thanks Dave! now i fully understood how the circuit works. we just didn't have the same protocol with regards to the terminology "open", now i know.
i find this site a lot informative and very helpful. thanks
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by Gary Elinoff