Hey guys, in studying asynchronous circuits, i got thinking about what actually constitutes hazards etc. The whole idea about implication charts etc it to take into account all possible states. But when a normal combinational circuit is used, how many levels of logic does there have to be before errors are likely to occur? (due to the latency in a particular level)

For example, for creating an edge detector we were given a simple schematic of a signal going through a NOT gate and being anded with the original. The output of which would create a momentary spike upon switching. Obviously this would cause a problem with every asynchronous circuit if this was not a simplified schematic. SO my question is how many levels (how many series' of cascaded gates) would have to be used before problems like these have to be considered? Is there a name for this particular type of hazard?

 

Hello,

There is some information on asynchone circuits in the EDUCYPEDIA.
http://www.educypedia.be/electronics/digitacounters.htm

There are more pages on digital electronics over there:

Digital electronics:
Arithmetic circuits D/A-A/D converters Number systems Codes and decoders Flip flops Technology Counters and registers General overview Technology-CMOS Digital logic Memories Technology-TTL Timers and oscillators

Greetings,
Bertus

 

Thanks for the links bertus, i had a look at some of them but i couldnt really find what i was looking for. I did stumble upon this however:
http://meseec.ce.rit.edu/eecc341-winter2001/341-1-9-2002.pdf

which deals with exactly the problem that i was referring to. So if anyone else was curious about this have a read.

Cheers

 

Hello,

The delays may even vary with the powersupply voltage and load capacity.
See the attached datasheet about the Cmos digital family.

Greetings,
Bertus

 

And by quite a large amount as well! asynchronous circuits must be very tricky to implement glitch free. The only asynchronous circuit i've ever had to make was a simple counter... i wouldnt like to implement anything complicated!

 

As you've already found out, two levels are enough to create a hazard. It is tricky to design an asynchronous circuit, but it is not impossible. There are automation tools to alleviate the problem, to an extend, and also rigid topologies. It does add up to the circuit complexity though.

I think it would be pretty hard to realise all the advantages of asynchronous circuits and compete with traditional clocked circuits, when the size and complexity are not in proportion with clocked circuits.

If you are interested, have a look at Handshake Solution (spin-off of Philips) which has an asynchronous ARM core design. Philips also used to have an asynchronous 8051 core. Manchester University (formerly UMIST) also has AMULET, which is a research development of asynchronous ARM cores.

 

Cool thanks for that.