Hi Guys

I have drawn up this little diagram of a project I wish to implement but don't know if its feasible...

basically it can be taken as a few separate stages. correct as necessary.....!

1/ atmel code communicates via i2c to the dc/dc controller. requests voltages on the registers of the lp3906. the linear output is not needed (yet).

2/ the power from the buck outputs is used to power up a fpga, at whatever voltages are needed.

clock management is also needed to sync the two devices?

3/ now, with the fpga active, it also has a i2c core implemented to communicate its activity to the atmel....

4/ another logic block on the fpga like a alu causes the fpga activity to fluctuate, the fpga requests voltage changes to the atmel..

depending on its requirements, and so forth.

5/ the atmel sends these new requirements on the fly to the lp3906. and in turn these are sent back to the fpga.

... dynamic voltage management....

what do you guys make of this... would it work even..?!

i am aware of the complications on voltage requirements on the fpga...

i could possible use some look up table to store voltage(s) on the atmel memory so it knows which levels are needed.

also i could maybe use a wdt on the atmel to monitor activity on the fpga (to sense changes in voltage).

thanks for looking!

 

That looks good to me.
You should think about the ramp time between different voltages, as it may produce harmonics on FPGA the supply lines if it´s too fast.
I am still not sure why does the FPGA need different voltages throughout the time, is there some realtion between propagation delay and voltage? It looks to me that to reduce power consumtion you can simply keep the voltage at the lowest level.
Or does the FPGA also alter its working frequency?