Your assignment is to do a paper design of an octal-to-7-segment common cathode decoder
for digits 0, 2, 3, 5, 6 and 7 using the least possible number of NAND gates. You are to assume
that only these octal digits are applied to the inputs of the decoder, i.e. combinations for digits 1 and
4 are never applied

im using multisim btw ...... can anyone help me with the diagram cause i know nuts bout it......

 

The homework service is two forums down on the left...

 

hi... so i posted in the wrong forum? can you help me move it or something.....?? thanks..

 

homework forum rules ... http://forum.allaboutcircuits.com/showthread.php?t=3002

 

help needed please .... thanks...

 

Hello,

Please show us your efforts and tell us where you got problems.

Bertus

 

Basically we will try to answer questions in such a way that you learn. If we just did the homework you would get no benefit from it. So as Bertus says, you have to show us your work first, then explain where you are having problems.

 

Start by drawing up a truth table.
Then derive some logic equations.
Simplify these equations. There are various ways of doing this.
Karnaugh map is one way.
Draw circuit.
Test with simulator.

Or of course you could Google (but that would be cheating).